ComplexDeinterleavingPass.cpp:1849:3: error: default label in switch which covers all enumeration values

This reverts commit 116953b8.

As the extension list continues to grow it probably makes sense
to use a binary search rather than linear search. Sorting the strings
will make this possible.

This also avoids any question about where to add new strings in
the tables.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D153170

For the secondary allocation we don't need poison and fill memory if we
skip quarantine, and we don't need to poison after quarantine. In both
cases the secondary allocator will unmap memory and unpoison the shadow
from get_allocator().Deallocate().

Depends on D153496.

Reviewed By: thurston

Differential Revision: https://reviews.llvm.org/D153497

The select-of-different-exp pattern appears in the device
libraries. I haven't seen the select-of-values case.

getExpr is missing a check to make sure the result is invertible.
This can lead to incorrect results, so return nullptr in those cases
like in other places in IVUsers.

Fixes #62660.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D153202

There is a gap between running opt -Oz and running opt -passes="OZ_PASSES" where OZ_PASSES is taken from running opt -Oz -print-pipeline-passes.

One of the reasons causing this is that -Oz uses non-default setting for LoopRotate but LoopRotate does not expose its settings when printing the pipeline.

This commit fixes this by exposing LoopRotates parameters.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D153437

Revert "[llvm-exegesis] Introduce Subprocess Executor Mode"

This reverts commit 5e9173c4.
This reverts commit 4d618b52.

Reverting the PID commit as it is currently breaking MinGW builds and
the way I'm checking for the presence of pid_t needs to be fixed and I
need to do some testing. The subprocess executor mode patch is a
dependent patch so also needs to be reverted and also needs some work as
it is currently failing tests where libpfm is installed and the kernel
version is less than 5.6.

Fix build failure on windows system with msvc toolchain

Reviewed By: ellis

Differential Revision: https://reviews.llvm.org/D153318

D152759 introduced the Android .zip so file support, but it only considered
POSIX path. The code also runs on Windows, so the path could be Windows path.
Support both patterns on Windows.

Differential Revision: https://reviews.llvm.org/D153390

Reviewed By: thurston

Differential Revision: https://reviews.llvm.org/D153496

Since the scheduling resources for reductions and ordered reductions now
account for LMUL and SEW, we can modify the Latency and ResourceCycles
for these resoruces.

* Most reductions take a total of approx `vl*SEW/DLEN + 5*(4 + log2(DLEN/SEW))`
  cycles.
* Ordered floating-point reductions take a total of approx `5*vl` cycles.

This commit re-commits 208fc34c. It was
failing because it used wrong version of SchedSEWSet.

Differential Revision: https://reviews.llvm.org/D153474

Differential Revision: https://reviews.llvm.org/D146148

This reverts commit 208fc34c.

Reverting because build failure.

Since the scheduling resources for reductions and ordered reductions now
account for LMUL and SEW, we can modify the Latency and ResourceCycles
for these resoruces.

* Most reductions take a total of approx `vl*SEW/DLEN + 5*(4 + log2(DLEN/SEW))`
  cycles.
* Ordered floating-point reductions take a total of approx `5*vl` cycles.

Differential Revision: https://reviews.llvm.org/D153474

* Unit-stride loads and stores can operate at the full bandwidth of the
memory pipe. The memory pipe is DLEN bits wide.

* Strided loads and stores operate at one element per cycle and should
be scheduled accordingly.

* Indexed loads and stores operate at one element per cycle, and they
stall the machine until all addresses have been generated, so they
cannot be scheduled.

* Unit stride seg2 load is number of DLEN parts

* seg3-8 are one segment per cycle, unless the segment is larger
than DLEN in which each segment takes multiple cycles.

Differential Revision: https://reviews.llvm.org/D153475

Also moves the wait-until-inbox-changes test into a shared method.

Reviewed By: jhuber6

Differential Revision: https://reviews.llvm.org/D153573

Almost NFC, as blocks over max quarantine size will trigger immediate
drain anyway. In followup patches we can optimize passthrough case.

Reviewed By: thurston

Differential Revision: https://reviews.llvm.org/D153495

The `__DATA,xray_instr_map` section has label differences like
`.quad Lxray_sled_0-Ltmp0` that is represented as a pair of UNSIGNED and SUBTRACTOR relocations.

LLVM integrated assembler attempts to rewrite A-B into A-B'+offset where B' can
be included in the symbol table. B' is called an atom and should be a
non-temporary symbol in the same section. However, since `xray_instr_map` does
not define a non-temporary symbol, the SUBTRACTOR relocation will have no
associated symbol, and its `r_extern` value will be 0. Therefore, we will see
linker errors like:

    error: SUBTRACTOR relocation must be extern at offset 0 of __DATA,xray_instr_map in a.o

To fix this issue, we need to define a non-temporary symbol in the section. We
can accomplish this by renaming `Lxray_sleds_start0` to `lxray_sleds_start0`
("L" to "l").

`lxray_sleds_start0` serves as the atom for this dead-strippable subsection.
With the `S_ATTR_LIVE_SUPPORT` attribute, `ld -dead_strip` will retain
subsections that reference live functions.

Special thanks to Oleksii Lozovskyi for reporting the issue and providing
initial analysis.

Differential Revision: https://reviews.llvm.org/D153239

Replace getAs with castAs and add assert if needed.
Differential revision: https://reviews.llvm.org/D153236

Adds the capability to recognize SelectInst that appear in the IR.
These instructions are generated during scalable vectorization for reduction
and when the code contains conditions inside the loop body or when
"-prefer-predicate-over-epilogue=predicate-dont-vectorize" is set.

Differential Revision: https://reviews.llvm.org/D152558

Signed-off-by: Jun Zhang <jun@junz.org>

Differential Revision: https://reviews.llvm.org/D153572

This makes the interface less error prone. The acquire was previously
forgotten. Release is currently missing if recv() is the last operation made
before close.

Reviewed By: jhuber6

Differential Revision: https://reviews.llvm.org/D153571

The GPRF64 has the same spill size as GPR and is only used for RV64.
There's no real reason to have it as a separate class other than
for type inference for isel patterns in tablegen.

This patch adds f64 to the GPR register class when XLen=64. I use
f32 when XLen=32 even though we don't make use of it just to avoid
the oddity.

isel patterns have been updated to fix the lack of type infererence.

I might do similar for GPRF16 and GPRF32 or I might change them to
use an optimized spill size instead of always using XLen.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D153110

For https://bugs.chromium.org/p/llvm/issues/detail?id=46

Differential Revision: https://reviews.llvm.org/D153473

According to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
these were ratified in April 2023.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D153161

This commit ensures that an empty list of result attributes is not
imported as an empty `ArrayAttr`. Instead, the attribute is just not
added to the `LLVMFuncOp`.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D153553

Required for phase ordering changes to not regress Rust code with D145265.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D153391

Helps with debugging issues caught by the verifier.

Plumbed through both normal clang compile and ThinLTO.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D153468

This is a similar change to one proposed for GCC:
https://inbox.sourceware.org/gcc-patches/20230414170942.1695672-1-patrick@rivosinc.com/

The changes in this patch are based on the proposal by Hans Boehm to more
closely match the intended semantics for sequentially consistent stores
and to allow some platforms to avoid an ABI break when switching to more
performant atomic instructions. Platforms that have already compiled
code using the existing mappings will also have more time to gradually
replace that code in preparation of the switch.

Further details can be found in the psABI proposal:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378.

This patch implements a mapping that is stronger than the one outlined in table
A.6 of the RISC-V unprivileged spec to be future compatible with table A.7 of
the same document. The related discussion can be found at
https://lists.riscv.org/g/tech-unprivileged/topic/risc_v_memory_model_topics/92916241

The major change to RISC-V code generation is that we will now emit a trailing
fence for sequentially consistent stores.

The new code sequence should have the following form:
```
fence rw,w; s{b|h|w|d}; fence rw,rw;
```

Other changes and optimizations like using amoswap will be handled separately.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D149486

This patch adds the LLVM-side plumbing for the following relocations:
- R_ARM_THM_ALU_ABS_G0_NC
- R_ARM_THM_ALU_ABS_G1_NC
- R_ARM_THM_ALU_ABS_G2_NC
- R_ARM_THM_ALU_ABS_G3

(see section 5.6.1.5, Static Thumb16 relocations, of the AArch32 ELF Arm ABI:
https://github.com/ARM-software/abi-aa/blob/844a79fd4c77252a11342709e3b27b2c9f590cf1/aaelf32/aaelf32.rst#5615static-thumb16-relocations)

Which can respectivly be generated by prefixing assembly symbols with:
- :lower0_7:
- :lower8_15:
- :upper0_7:
- :upper8_15:

LLD support for these relocations will be added in a follow-up patch

Reviewed By: john.brawn, MaskRay

Differential Revision: https://reviews.llvm.org/D149443

This flag enables Fortran 2003 polymorphism. It is marked experimental
and not included in --help.

Reviewed By: tblah, awarzynski

Differential Revision: https://reviews.llvm.org/D153281

This reverts commit d8851384.

Reason: Applied the fix for the Asan buildbot failures.

When eliding an argument copy, we need to update the chain to ensure
the argument reads are performed before later writes. However, the
code doing this only handled this for the first part of the argument.
If the argument had multiple parts, the chains of the later parts were
dropped. Make sure we preserve all chains.

Fixes https://github.com/llvm/llvm-project/issues/63430.

Doesn't really matter for the larger purpose of the test, but
avoid the use of undef indices and instead use the loop induction
variable as index, which is what was likely intended here.

Add lowering support for the use_device_ptr and use_Device_addr clauses for the Target Data directive.

Depends on D152822

Differential Revision: https://reviews.llvm.org/D152824

Minor reordering of clauses in the assembly format for Target Data op to make it closer to the OpenMP standard.

Differential Revision: https://reviews.llvm.org/D152822