These warnings came up with gcc-11.3.0.

This change was wrongly reverted and re-broke the Windows buildbot.

Sponsored by: The FreeBSD Foundation

Try to always send vCont packets and include the PID in them if running
multiprocess.  This is necessary to ensure that with the upcoming full
multiprocess support always resumes the correct process without having
to resort to the legacy Hc packets.

Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D131758

This reverts commit 853bb192.

Reviewed By: thieta

Differential Revision: https://reviews.llvm.org/D131650

Similar to D76746 (ARM), D76754 (AArch64), D77018 (RISCV)  and
llvmorg-11-init-6967-g152d14da (x86)

Differential Revision: https://reviews.llvm.org/D132119

This patch only add %pc_hi20/%pc_lo12/%plt relocations in order
to be able to generate gnu ld linkable relocation file for the
`hello world` IR :
```
@.str = private unnamed_addr constant [14 x i8] c"Hello world!\0A\00", align 1

define dso_local signext i32 @main() nounwind {
entry:
  %call = call signext i32 (ptr, ...) @printf(ptr noundef @.str)
  ret i32 0
}

declare dso_local signext i32 @printf(ptr noundef, ...)
```

This patch also updates some test cases due to new modifiers introduced.
New test: test/MC/LoongArch/Relocations/relocations.s

Differential Revision: https://reviews.llvm.org/D132108

Reviewed By: xen0n, SixWeining

Differential Revision: https://reviews.llvm.org/D132198

Following the comment's thread of D117235, I added checks for the widening + splitting case, which also causes a split with one of the resulting vectors to be empty. Due to the same issues described in that same thread, the `fixed-vectors-strided-store.ll` test is missing the widening + splitting case, while the same case in the `strided-vpload.ll` test requires to manually split the loaded vector.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121784

Adds a builtin that serves as an optimization hint to apply specific optimized
DAG mutations during scheduling. This also disables any other mutations or
clustering that may interfere with the desired pipeline. The first optimization
strategy that is added here is designed to improve the performance of small gemm
kernels on gfx90a.

Reviewed By: jrbyrnes

Differential Revision: https://reviews.llvm.org/D132079

Wasn't handling correctly creating DW_AT_rnglists_base in UnitDie when
converting access pattern for DW_AT_ranges from offset to index for DWARF5.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D132087

This patch combines D129166 (to always pick the just-built libc++) and
D132257 (to allow customizing the libc++ for testing). The common goal
is to avoid picking up an unexpected libc++ for testing.

Differential revision: https://reviews.llvm.org/D132263

This change renames this method match its original name and the name
used in the wasm linker.

Back in d8f8abbd the ELF SymbolTable
method `getSymbols()` was replaced with `forEachSymbol`.

Then in a2fc9644 `forEachSymbol` was
replaced with a `llvm::iterator_range`.

Then in e9262edf we came full circle
and the `llvm::iterator_range` was replaced with a `symbols()` accessor
that was identical the original `getSymbols()`.

`getSymbols` also matches the name used elsewhere in the ELF linker as
well as in both COFF and wasm backend (e.g. `InputFiles.h` and
`SyntheticSections.h`)

Differential Revision: https://reviews.llvm.org/D130787

Currently ExtractAPI only emits availability information for the
current platform. This makes it easy for clients to get all availability
information for a given symbol in one invocation as opposed to having to invoke
clang once per-platform and then merge the symbol-graphs.

Differential Revision: https://reviews.llvm.org/D130918

This reverts commit 01e3a376.
Breaks tests on mac and win, see comments on https://reviews.llvm.org/D132255

This addresses a change in behavior of the bugprone-sizeof-expression
checker after upstream commit 15f3cd6b, which cleaned up
ElaboratedType sugaring in the AST.  This restores (mostly) the
beahvior of the checker prior to that commit, which may or may not have
been consistent with the intent of the checker, but at least gave a
tolerable level of what users would consider false positives.

Bug: https://github.com/llvm/llvm-project/issues/57167

Reviewed By: mizvekov, aaron.ballman

Differential Revision: https://reviews.llvm.org/D131926

Change-Id: Ibe5aad77ad00977134aa7fa67efbbd6bd725fd79

A couple of instances of iterating over maps snuck in while the bot was
down; fix them to use maps with deterministic iteration.

This reverts commit 7ba14b86.

This patch enables expansion or custom lowering for some integer
condition codes so that any xori that is needed is created before
the last DAG combine to enable optimization.

I've seen cases where we end up with
(or (xori (setcc), 1), (xori (setcc), 1)) which we would ideally
convert to (xori (and (setcc), (setcc)), 1). This patch doesn't
accomplish that yet, but it should allow us to add DAG
combines as follow ups. Example https://godbolt.org/z/Y4qnvsq1b

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D131729

Author: vdonaldson

Differential Revision: https://reviews.llvm.org/D132259

This should cut down on the visual noise when reducing. Still keep output when we run a pass or when we successfully reduce.

Notably, this also suppresses redirecting the test output to stdout/stderr.

Reviewed By: regehr

Differential Revision: https://reviews.llvm.org/D131922

SDNode.

How:
1) Add AArch64ISD::PMULL SDNode, and extend aarch64_neon_pmull intrinsic
   tablegen pattern for this SDNode.
2) For aarch64_neon_pmull64, canonicalize i64 operands to v1i64 vectors
   during legalization.
3) For {aarch64_neon_pmull, aarch64_neon_pmull64}, combine intrinsic to
   SDNode.

Why
1) Adding the SDNode makes it easier to canonicalize i64 inputs (required by
   aarch64_neon_pmull64) to vector inputs. Vector inputs carries lane
   information, which helps dag-combiner to combine nodes (e.g. rewrite to a
   better node to prepare for instruction selection) and instruction-selection
   to emit instructions that use higher-half inputs in place
   (i.e., no need to move lane 1 content to lane 0).
2) Using the SDNode for aarch64_neon_pmull64 is NFC, yet without this we
   have to move the definition of {PMULLv1i64, PMULLv2i64} out of its
   current group of records without gains.

Test cases are commented with what is being tested in
`aarch64-pmull2.ll` and `pmull-ldr-merge.ll` under directory
`llvm/test/CodeGen/AArch64`.

Differential Revision: https://reviews.llvm.org/D131047

Differential Revision: https://reviews.llvm.org/D131045

Differential Revision: https://reviews.llvm.org/D132212

Look for both kinds of slashes in include paths output from the
compiler.

Use "diff -w" to do a whitespace insensitive comparison, to ignore
differences in line endings (the python script writes to stdout
in text mode, with crlf newlines).

Differential Revision: https://reviews.llvm.org/D129428