This causes asserts to fire:

  llvm/lib/Analysis/ValueTracking.cpp:4262:
  std::tuple<Value *, FPClassTest, FPClassTest> llvm::fcmpImpliesClass(CmpInst::Predicate, const Function &, Value *, const APFloat *, bool):
  Assertion `(RHSClass == fcPosNormal || RHSClass == fcNegNormal || RHSClass == fcPosSubnormal || RHSClass == fcNegSubnormal) && "should have been recognized as an exact class test"' failed.

See comments on the PR.

> Previously we could recognize exact class tests performed by
> an fcmp with special values (0s, infs and smallest normal).
> Expand this to recognize the implied classes by a compare with a general
> constant. e.g. fcmp ogt x, 1 implies positive and non-0.
>
> The API should be better merged with fcmpToClassTest but that
> made the diff way bigger, will try to do that in a future
> patch.

This reverts commit dc3faf0e.

Similar to #70635, this expands the handling of integer to fp
conversions. The code is very similar to the float->integer conversions
with types handled oppositely. There are some extra unhandled cases
which require more handling for ASR operations.

This patch lowers `sdiv x, +/-2**k` to `add + select + shift` when the
short forward branch optimization is enabled. The latter inst seq
performs faster than the seq generated by target-independent
DAGCombiner. This algorithm is described in ***Hacker's Delight***.

This patch also removes duplicate logic in the X86 and AArch64 backend.
But we cannot do this for the PowerPC backend since it generates a
special instruction `addze`.

This reverts commit fd5206cc.

Fixing the test case would require some awkard %if use that I'm not
sure would even work, or splitting it into 2 copies that are almost
identical.

Instead, always add -m for clang, which allows it for all targets,
but not for gcc which does not.

There are three changes present in this PR.

1. Use github packages for libcxx-builder rather than dockerhub.

The ldionne/libcxx-builder image will now be hosted at
ghcr.io/libcxx/libcxx-builder. This has the benefit of allowing members
of the github org to push new versions.

In the future I hope to add github actions to rebuild the image as
needed.

2. Add docker-compose file

The compose file allows to to specify the package repository, so that
users can simply write 'docker compose build' and 'docker compose push'.

It also gives us a centralized place to manage version arguments which
change frequently.

3. Use non-shell CMD form.

This may help the google libcxx builders disconnect more gracefully as
the shell form of CMD may eat the shutdown signal. I'm hoping this
corrects inaccurate agent counts from the buildkite API, since when the
VM's terminate, they do so without signaling it to buildkite, whi...

This patch skips default privatization for crashing cases like
namelists, reduction instrinsics, and structure constructor.

Fixes: https://github.com/llvm/llvm-project/issues/67332,
https://github.com/llvm/llvm-project/issues/66454, and
https://github.com/llvm/llvm-project/issues/65569



Co-Authored-By: kiranchandramohan <kiran.chandramohan@arm.com>

This reverts commit 7c3603e1.

Turns out when you ask for "clang" it also uses the GCC Builder class,
so I need to update some tests.

This option is definitely needed for x86_64, and is valid for PowerPC
and s390x too.

I'm using "in" because on Armv8 Linux the uname is actually "armv8l"
not just "arm".

The test added causes some buildbot failures:
- https://lab.llvm.org/buildbot/#/builders/17/builds/45077
https://lab.llvm.org/buildbot/#/builders/96/builds/48277

Remove the test for now to make the builtbots happy, and will re-add it after
investigation.

Fixed:

1. Maximum register pressure calculation at the instruction level. 
Previously max RP included both def and use of registers of an
instruction. Now maximum RP includes _uses_ and _early-clobber defs_.

2. Uses were incorrectly tracked and this resulted in a mismatch of
live-in set reported by LiveIntervals and tracked live reg set when the
beginning of the block is reached.

Interface has changed, moveMaxPressure becomes deprecated and
getMaxPressure, resetMaxPressure functions are added. reset function
seem now more consistent.

The previous one must have been an expiring one, this new
one is a non-expiring one that Chandler generated some time ago.

Patch 1/3 of the transition to use the HLFIR step by default in lowering
as described in
https://discourse.llvm.org/t/rfc-enabling-the-hlfir-lowering-by-default/72778/7

This option will allow to lower code without the HLFIR step during a
grace period as described in the RFC. It is not meant to be a long term
switch for flang.

When returning variable declaration values, try to get the value
directly instead of always going through a Pointer.

This reverts commit f7bbb586 which caused
another formatting failure in polly.

Software prefetching helps recover performance when hardware prefetching
is disabled. The 'LIBC_COPT_MEMSET_X86_USE_SOFTWARE_PREFETCHING' compile
time option allows users to use this patch.

Also fixed another bug in isStartOfName().

Address the FIXME, this will allow lldb to print all fields of the
generated coroutine frame structure.

Fixes #69309.

This register is a pseudo register but mirrors the architectural
register's contents. See:
https://developer.arm.com/documentation/ddi0616/latest/

For the full details. Example output:
```
(lldb) register read svcr
    svcr = 0x0000000000000002
         = (ZA = 1, SM = 0)
```

This reverts commit d62f0404.
Some cuda buildbots start failing.

The change implements lowering of `get_fpenv`, `set_fpenv` and
`reset_fpenv`.

Differential Revision: https://reviews.llvm.org/D81843

This is a Linux pseudo register provided by the NT_ARM_TAGGED_ADDR_CTRL
register set. It reflects the value passed to prctl
PR_SET_TAGGED_ADDR_CTRL.

https://docs.kernel.org/arch/arm64/memory-tagging-extension.html

The fields are made from the #defines the kernel provides for setting
the value. Its contents are constant so no runtime detection is needed
(once we've decided we have this register in the first place).

The permitted generated tags is technically a bitfield but at this time
we don't have a way to mark a field as preferring hex formatting.

```
(lldb) register read mte_ctrl
mte_ctrl = 0x000000000007fffb
         = (TAGS = 65535, TCF_ASYNC = 0, TCF_SYNC = 1, TAGGED_ADDR_ENABLE = 1)
```

(4 bit tags mean 16 possible tags, 16 bit bitfield)

Testing has been added to TestMTECtrlRegister.py, which needed a more
granular way to check for XML support, so I've added hasXMLSupport that
can be used wi...

We added LoopDataPrefetch in 9bb69c1d but Scalar is not linked.

Cast StackSaveAreaPtr, GrRegSaveAreaPtr, VrRegSaveAreaPtr to pointers to
fix assertions in getShadowOriginPtrKernel().

Fixes: https://github.com/llvm/llvm-project/issues/69738

Patch by Mark Johnston.

si-wqm sometimes needs to save the LiveMask in the entry block. Later
on, while looking for a place to enter WQM/WWM, it unconditionally
skips over the first COPY instruction in the entry block. This is
incorrect for functions where the LiveMask doesn't need to be saved, and
therefore the first COPY is more likely a COPY from a function argument
and might need to be in some non-exact mode.

This patch fixes the issue by also checking that the source of the COPY
is the EXEC register.

This produces different code in 3 of the existing tests:

In wwm-reserved.ll, a SGPR copy is now inside the WWM area rather than
outside. This is benign.

In wave32.ll, we end up with an extra register copy. This is because
the first COPY in the block is now part of the WWM block, so
si-pre-allocate-wwm-regs will allocate a new register for its
destination (when it was outside of the WWM region, the register
allocator could just re-use the same register). We might be able to
improve this in si-pre-allocate-wwm-regs but I haven't looked into it.

The same thing happens in dual-source-blend-export.ll, but for that
one it's harder to see because of the scheduling changes. I've uploaded
the before/after si-wqm output for it here:
https://reviews.llvm.org/differential/diff/553445/

Differential Revision: https://reviews.llvm.org/D158841

Fixes #65034 by skipping copy of host-association information if the
concerned symbol is missing from the inner construct

If `page(dest) - page(pc)` is 0xfffffffffff000, i.e. page(pc) is next
to page(dest), and lo12(dest) > 0x7ff, correct %pc64_lo12 and %pc64_hi12
should be both -1 (which can be checked with binutils) but they are both
0 on lld. This patch adds such a test showing lld's incorrect behaviour
and following patch will fix this issue.

MCInstrAnalysis can return properties of instructions (e.g., isCall(),
isBranch(),...) based on the informations that MCInstrDesc can get from
*InstrInfo*.td files. These infos are based on opcodes only, but JIRL
can have different properties based on different registers used.

So this patch refines several MCInstrAnalysis methods: isTerminator,
isCall,isReturn,isBranch,isUnconditionalBranch and isIndirectBranch.

This patch also allows BOLT which will be supported on LoongArch later
to get right instruction infos.

This patch adds an integration test demonstrating the first e2e example
lowering a linalg.matmul to SME via vector.outerproduct.

The test uses a 'linalg.matmul_transpose_a' rather than 'linalg.matmul'
since the latter emits a 'vector.transfer_read' with a vector type of
'vector<[4]x1xf32>' that can't be currently lowered via generic (SVE)
path, since it has leading scalable dim.

This patch extends the lowering of vector.transfer_write in
VectorToArmSME to support in-flight transpose via SME vertical store.

Currently we have an optimization that if the ADR points to the same
function we might skip it's relaxation. But it doesn't take into account
that BF might be split, in such situation we still need to relax it. And
just in case also relax if the initial BF size is >= 1MB.
Fixes #71822