Reviewed By: ldionne, #libc

Spies: libcxx-commits

Differential Revision: https://reviews.llvm.org/D137283

Broadwell/Haswell were completely overriding the class defs - we can remove those overrides entirely by just choosing better class defs (plus a fix for missing mmx folded load).

The `target_link_libraries()` call operates on `gtest_main` rather than
`llvm_gtest_main`.  I think it was missed while prefixing all the tools
in 38151a08.

Differential Revision: https://reviews.llvm.org/D137080

Unswitching adjusts the CFG in ways that may invalidate cached loop
dispositions. Clear all cached block and loop dispositions during
trivial unswitching. The same is already done for non-trivial
unswitching.

Fixes #58751.

The WriteCvtSD2SS/WriteCvtPD2PS* classes were mostly unused as the models were needlessly overriding all instructions - in some cases the folded pattern overrides were entirely missing (but I've confirmed they just have an additional Port23 use)

There were a couple of typos (confirmed with Agner/uops.info) - Skylake/Icelake uses Port5+Port01 for XMM/YMM, Skylake uses Port5+Port05 for ZMM but Icelake uses Port5+Port0

This mirrors what we have done in the classic algorithms

Reviewed By: ldionne, #libc

Spies: libcxx-commits

Differential Revision: https://reviews.llvm.org/D137186

SS2SI64 conversions use Port0/Port01/Port5 (with/without truncation), but SS2SI32 only uses Port0/Port01 like SD2SI32/SD2SI64

Represent the select type statement + type guard statement
the same way the select case statement and case statement are represented.
controlSuccessor was not correctly attributed to the next type guard stmt.

Reviewed By: PeteSteinfeld, vdonaldson

Differential Revision: https://reviews.llvm.org/D137460

These were lost when they were converted from instregex to instrs

Replaces hard coded uses of WriteVPMOV256 for all the vector truncations instructions

We still need to work out how to fix folded stores (see Issue #36236)

[X86] Add missing ReadAfterFold attributes from CVTSD2SSrm/CVTSS2SDrm to match the AVX + _Int equivalents

This was never added in D52886, probably because the defs were already missing the old ReadAfterLd attribute, but they do exhibit the same behaviour of reading the dst reg after the load.

Just use the default WriteCvtSS2I/WriteCvtSD2I folded variants (already used by the VCVTSS2SI/VCVTSD2SI AVX variants).

Confirmed with agner and uops.info - there should be no difference between the SSE/AVX1 variants in folded load latency

Broadwell, Haswell and SkylakeClient were completely overriding the WriteCvtI2PD defs - we can remove those overrides entirely by replacing the unused WriteCvtI2PD values

There's plenty more of these in the scheduler models - I'm looking at improving warnings in llvm-tblgen to catch them all

[mlir] Add `populateFunctionOpInterfaceTypeConversionPattern` version which operates on any `FunctionOpInterface`

Exisitng version is always limited to some specific op.

Differential Revision: https://reviews.llvm.org/D137469

The links are all now from a "Developer Guides" page which is linked from the
main side bar.

Remove trailing whitespaces in MemRefOps.td. NFC.

This patch replaces the backing file path key to "file_path" to keep it
consistent.

rdar://101652618



Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>

It can happen that the originator of a crash report doesn't have access
to certain images. When that's the case, ReportCrash won't show the
source info in the crash report stack frames, but only the stack address
and image name.

This patch fixes a bug in the crashlog stackframe parser regular
expression to optionally match the source info group.

rdar://101934135

Differential Revision: https://reviews.llvm.org/D137466



Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>

`C1 - ((C3 - X) & C2) --> (X & C2) + (C1 - (C2 & C3))`
when:
    (C3 - ((C2 & C3) - 1)) is pow2 &&
    ((C2 + C3) & ((C2 & C3) - 1)) == ((C2 & C3) - 1) &&
    C2 is negative pow2 || (C3 - X) is nuw

https://alive2.llvm.org/ce/z/HXQJV-

Fix: #58523

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D136582

Add add_with_carry to builtin wrapper to be used by UInt class.

Reviewed By: orex

Differential Revision: https://reviews.llvm.org/D137453

We were missing DISubRangeAttr in the type switch. This
also updates a few of the range parameters to be optional.

The KeyTy of attribute/type storage classes provide enough information for
automatically implementing the necessary sub element interface methods. This
removes the need for derived classes to do it themselves, which is both much
nicer and easier to handle certain invariants (e.g. null handling). In cases where
explicitly handling for parameter types is necessary, they can provide an implementation
of `AttrTypeSubElementHandler` to opt-in to support.

This tickles a few things alias wise, which annoyingly messes with tests that hard
code specific affine map numbers.

Differential Revision: https://reviews.llvm.org/D137374

The first result of the extract_strided_metadata operation is a MemRef,
not a naked pointer.
This patch fixes the lowering of this operation in MemRefToLLVM so that
we properly materialize the full MemRef structure and not just the base,
naked, pointer.

Differential Revision: https://reviews.llvm.org/D137364

We can use SRLI by C to clear LSBs followed by a SLLI_UW.

But I can not reproduce the problem on my local machine. My local machine run:

222 0x5a6780
222 0x7fffbef9400e
222 0x5a677e 0x5a6780 0x7fffbef936c8
222 0x376f8e 0x376f90 0x7fffbef94008
222 0x281f20
222 0x7fffbef9400e
PASSED

Previously, we only checked for duplicate zero entries when merging a
MemOPSize table (see D92074), but a user recently provided a reproducer
demonstrating that other entries can also be duplicated. As demonstrated
by the test in this patch, PGOMemOPSizeOpt can potentially generate
invalid IR for non-zero, non-consecutive duplicate entries. This seems
to be a rare case, since the duplicate entry is often below the
threshold, but possible. This patch extends the existing warning to
check for any duplicate values in the table, both in the optimization
and in llvm-profdata.

Differential Revision: https://reviews.llvm.org/D136211

[mlir][sparse] fix sparse tensor rewriting patterns that do not propagate sparse tensor SSA properly.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D137468

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D137463

inc/dec are not add/sub of 1.

In `MLInlineAdvisor::getAdviceImpl`, we call `getCachedFPI` twice, once
for the caller, once for the callee, so the second may invalidate the
reference obtained by the first because the underlying implementation of
the cache is a `DenseMap`. `std::map` doesn't have that problem.