This patch sets the text flag correctly for llvm-reduce files

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D138304

+/-0 is obviously foldable. Other non-special, non-subnormal
values are also probably OK. For denormal values, check
the calling function's denormal mode. For now, don't fold
denormals to the input for IEEE mode because as far as I know
the langref is still pretending LLVM's float isn't IEEE.

Also folds undef to 0, although NaN may make more sense. Skips
folding nans and infinities, although it should be OK to fold those
in a future change.

[RISCV][CodeGen] Chapter of vector instruction type corresponds with chapters in RISCV vector specification. NFC

The [vector spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc) is organized in chapters
based on instruction type. The comments in the tablegen marked the incorrect chapters. This change
updates the comments with the correct chapter numbers.

Differential Revision: https://reviews.llvm.org/D138311

This utility is useful when we need to know if shape is dynamic and
we don't have a Type itself.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D138267

When we have a precisely known VLEN, we can replace runtime usage of VLENB with compile time constants. This converts offsets involving both fixed and scalable components into fixed offsets. The result is that we avoid the csr read of vlenb, and can often fold the multiply as well.

Differential Revision: https://reviews.llvm.org/D137591

On x86 and AArch, SIMD instructions encode all of the scheduling information in the instruction
itself. For example, VADD.I16 q0, q1, q2 is a neon instruction that operates on 16-bit integer
elements stored in 128-bit Q registers, which leads to eight 16-bit lanes in parallel. This kind
of information impacts how the instruction takes to execute and what dependencies this may cause.

On RISCV however, the data that impacts scheduling is encoded in CSR registers such as vtype or
vl, in addition with the instruction itself. But MCA does not track or use the data in these
registers. This patch fixes this problem by introducing Instruments into MCA.

* Replace `CodeRegions` with `AnalysisRegions`
* Add `Instrument` and `InstrumentManager`
* Add `InstrumentRegions`
* Add RISCV Instrument and `InstrumentManager`
* Parse `Instruments` in driver
* Use instruments to override schedule class
* RISCV use lmul instrument to override schedule class
* Fix unit tests to pass empty instruments
* Add -ignore-im clopt to disable this change

A prior version of this patch was commited in 5e82ee53. 2323a4ee reverted
that change because the unit test files caused build errors. The change with fixes
were committed in b88b8307 but reverted once again e8e92c83 due to more
build errors.

This commit adds the prior changes and fixes the build error.

Differential Revision: https://reviews.llvm.org/D137440

Differential Revision: https://reviews.llvm.org/D133012

Reviewers: James Henderson, Esme Yi

Differential Revision: https://reviews.llvm.org/D135887

Without this, clang builds a binary for macOS on a macOS host, and
then the linker complains that it doesn't know the -q flag.

Differential Revision: https://reviews.llvm.org/D138306

"tac" doesn't exist on macOS, so this makes the test pass there.

Differential Revision: https://reviews.llvm.org/D138305

* Stop setting config.python_executable in Unit/lit.site.cfg.py.in.
  All other projects only set this in the main lit config, not in the
  one for unit tests. (Unit tests don't spawn Python.)
* Set config.python_executable to Python3_EXECUTABLE in main
  lit.site.cfg.py.in instead of PYTHON_EXECUTABLE. All other files
  did this in c4c3883b.
* Stop setting enable_abi_breaking_checks, enable_backtrace, enable_shared.
  Nothing in bolt's tests (or in lit) reads them.

Differential Revision: https://reviews.llvm.org/D138299

In 52f39853 the option LLDB_INCLUDE_TESTS was
moved above the inclusion of LLDBStandalone. This isn't a problem per-se, but
it changes the default value of LLDB_INCLUDE_TESTS in standalone builds.
LLDBStandalone explicitly sets LLVM_INCLUDE_TESTS to true, indicating that
for standalone builds this is considered the default behavior.
This patch restores said default behavior.

Differential Revision: https://reviews.llvm.org/D138237

When selectVOP3PMadMixModsImpl fails, it can still create new copy instr
via selectVOP3ModsImpl. When selectG_FMA_FMAD gives up, new copy instr
will remain dead but will not be automatically removed.
InstructionSelect does not check if instructions created during selection
are dead.
Such dead copy doesn't have register class on dst operand and causes crash.
Fix is to build copy when operands are being added to selected instruction.

Differential Revision: https://reviews.llvm.org/D138044

Before D114230, indirect moves used regular MOV opcodes and were
identified by having an implicit use of M0. Since D114230 they use
dedicated opcodes instead, so remove some old code that checks for
implicit uses of M0. NFCI.

Differential Revision: https://reviews.llvm.org/D138308

[Clang][CodeGen][AIX] Map __builtin_frexpl, __builtin_ldexpl, and __builtin_modfl to 'double' version lib calls in 64-bit 'long double' mode

Summary:
AIX library functions frexpl(), ldexpl(), and modfl() are for 128-bit IBM long double, i.e. __ibm128. Other *l() functions, e.g., acosl(), are for 64-bit long double. The AIX Clang compiler currently maps builtin functions __builtin_frexpl(), __builtin_ldexpl(), and __builtin_modfl() to frexpl(), ldexpl(), and modfl() in 64-bit long double mode which results in seg-faults or incorrect return values. This patch changes to map __builtin_frexpl(), __builtin_ldexpl(), and __builtin_modfl() to double version lib functions frexp(), ldexp() and modf() in 64-bit long double mode.

Reviewed by: hubert.reinterpretcast, daltenty

Differential Revision: https://reviews.llvm.org/D137986

This allows discard_block_engine to work on platforms that might not
provide a full <limits.h> header.

Differential Revision: https://reviews.llvm.org/D138212

[AArch64][SVE] Use PTRUE instruction instead of WHILELO if the range is appropriate for predicator constant.

While get_active_lane_mask lowering it uses WHILELO instruction,
but forconstant range suitable for PTRUE then we could issue PTRUE instruction
instead.

Differential Revision: https://reviews.llvm.org/D137547

See:
https://reviews.llvm.org/rGcf69895ab31b
https://reviews.llvm.org/D136352
https://reviews.llvm.org/D137410

This patch adds `parseBase64Bytes` to the parser. It attempts to avoid double-allocating the buffer by re-using the token's spelling directly and eliding the quotes if they exist. It also avoids extra allocations by using std::vector<char> in the API - something we should change when the llvm::decodeBase64 API changes.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D138090

`GetPropertyAtIndexAsArgs` returns true on success and false on failure. Right
now it returns the converted `size_t` returned from `GetArgs` which describes
the number of arguments in the argument list. So for empty argument lists
(`(size_t)0` -> `(bool)false`) this function always fails.

The only observable effect of this seems to be that empty arguments are never
propagated to the internal LaunchInfo for a process. This causes that once any
argument has been added to `target.run-args`, clearing `target.run-args` doesn't
have any effect.

Fixes issue #55568

Reviewed By: JDevlieghere, jingham

Differential Revision: https://reviews.llvm.org/D126057

Reviewed By: #libc, philnik, ldionne

Differential Revision: https://reviews.llvm.org/D138286

his is the SelectionDAG equivalent of D136470, and is thus an alternate patch to D128159.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.

This patch also includes an implementation for SPLAT_VECTOR as without it, the lane wise reasoning has no base case. The original patch which inspired this (D128159), also included STEP_VECTOR. I plan to do that as a separate patch.

Differential Revision: https://reviews.llvm.org/D137140

Unconditionally removing landing pads results in invalid IR,
if there is a different `invoke` that uses it. Update the code
to only remove the landing pad if the current invoke is the only
user. Also carefully avoid creating plain branches to bbs with
landing pads we couldn't remove.

Reviewed By: arsenm, aeubanks

Differential Revision: https://reviews.llvm.org/D138072

We don't modify them. Also use auto here since we already wrote the full
type in the cast.

ARCRegisterInfo::eliminateFrameIndex updated to fix build error caused by 32bd7571

The backward register scavenger has correct register
liveness information. PEI should leverage the backward register scavenger.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D137574

Added dimensions can be both static and dinamic. Mapped dimension should be the same in the input and the init.

Differential Revision: https://reviews.llvm.org/D138291

As seen in https://github.com/llvm/llvm-project/issues/55023 when a thin
archive is updated when not in the CWD, replacement does not work as
expected. This change fixes the relative file path comparison so the
correct files are updated.

Differential Revision: https://reviews.llvm.org/D138218

The zip/uzp (2-vector) instruction classes have the incorrect
register constraints and mark the destination as also being an
input. However, the instructions are fully destructive so I've
restructured the classes.

Differential Revision: https://reviews.llvm.org/D138288

Instead of importing constant expressions recursively, the revision
walks all dependencies of an LLVM constant iteratively. The actual
conversion then iterates over a list of constants and all intermediate
constant values are added to the value mapping. As a result, an LLVM IR
constant maps to exactly one MLIR operation per function. The revision
adapts the existing tests since the constant ordering changed for
aggregate types. Additionally, it adds extra tests that mix aggregate
constants and constant expressions.

Depends on D137416

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D137559

check, NFC