MOVi32imm + ANDWrr ==> ANDWri + ANDWri
MOVi64imm + ANDXrr ==> ANDXri + ANDXri

The mov pseudo instruction could be expanded to multiple mov instructions later.
In this case, try to split the constant operand of mov instruction into two
bitmask immediates. It makes only two AND instructions intead of multiple
mov + and instructions.

Added a peephole optimization pass on MIR level to implement it.

Differential Revision: https://reviews.llvm.org/D109963

Fixes bugprone-virtual-near-miss & performance-type-promotion-in-math-fn.

[clang-format][docs] mark new clang-format configuration options based on which version they would GA

Sometimes I see people unsure about which options they can use in specific versions of clang-format because
https://clang.llvm.org/docs/ClangFormatStyleOptions.html points to the latest and greatest versions.

The reality is this says its version 13.0, but actually anything we add now, will not be in 13.0 GA but
instead 14.0 GA (as 13.0 has already been branched).

How about we introduce some nomenclature to the Format.h so that we can mark which options in the
documentation were introduced for which version?

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D110432

Call RemoveMachineInstrFromMaps before erasing instrs.
repairIntervalsInRange will do this for you after erasing the
instruction, but it's not safe to rely on it because assertions in
SlotIndexes::removeMachineInstrFromMaps refer to fields in the erased
instruction.

This fixes asan buildbot failures caused by D110335.

Add the fir.save_result operation. It is use to save an
array, box, or record function result SSA-value to a memory location

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D110407



Co-authored-by: Jean Perier <jperier@nvidia.com>
Co-authored-by: Valentin Clement <clementval@gmail.com>

This reverts commit 8fdac7cb.

The issue causing the revert has been fixed a while ago in 60b85209.

Original message:

    Now that SCEVExpander can preserve LCSSA form,
    we do not have to worry about LCSSA form when
    trying to look through PHIs. SCEVExpander will take
    care of inserting LCSSA PHI nodes as required.

    This increases precision of the analysis in some cases.

    Reviewed By: mkazantsev, bmahjour

    Differential Revision: https://reviews.llvm.org/D71539

This patch emits DW_TAG_namelist and DW_TAG_namelist_item for fortran
namelist variables. DICompositeType is extended to support this fortran
feature.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D108553

Update the fir.insert_on_range operation. Add a better description,
builder and verifier.

This patch is part of the upstreaming effort from fir-dev branch.

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D110389



Co-authored-by: Jean Perier <jperier@nvidia.com>
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Valentin Clement <clementval@gmail.com>

Implement the final part of GET_COMMAND_ARGUMENT, i.e. the handling of
ERRMSG. This uses some of the infrastructure in stat.h and gets rid of
the magic numbers that we were using for return codes.

Differential Revision: https://reviews.llvm.org/D109814

Partial implementation for the second entry point for
GET_COMMAND_ARGUMENT. It handles the VALUE and STATUS arguments, and
doesn't touch ERRMSG.

Differential Revision: https://reviews.llvm.org/D109813

Implement the ArgumentLength entry point of GET_COMMAND_ARGUMENT. Also
introduce a fixture for the tests.

Note that this also changes the interface for ArgumentLength from
returning a 4-byte integer to returning an 8-byte integer.

Differential Revision: https://reviews.llvm.org/D109227

Add more information for test failures inspection.

[RFC: Add min/max ops](https://llvm.discourse.group/t/rfc-add-min-max-operations/4353)

I was following the naming style for Arith dialect in
https://reviews.llvm.org/D110200,
i.e. similar to DivSIOp and DivUIOp I defined MaxSIOp, MaxUIOp.

When Arith PR is landed, I will migrate these ops as well.

Differential Revision: https://reviews.llvm.org/D110540

In TwoAddressInstructionPass::processTiedPairs, update subranges of the
live interval for RegB as well as the main range.

This is a small step towards switching TwoAddressInstructionPass over
from LiveVariables to LiveIntervals. Currently this path is only tested
if you explicitly enable -early-live-intervals.

Differential Revision: https://reviews.llvm.org/D110526

After TwoAddressInstructionPass calls
TargetInstrInfo::convertToThreeAddress, improve the LiveIntervals repair
to cope with convertToThreeAddress creating more than one new
instruction.

This mostly seems to benefit X86. For example in
test/CodeGen/X86/zext-trunc.ll it converts:

  %4:gr32 = ADD32rr %3:gr32(tied-def 0), %2:gr32, implicit-def dead $eflags

to:

  undef %6.sub_32bit:gr64 = COPY %3:gr32
  undef %7.sub_32bit:gr64_nosp = COPY %2:gr32
  %4:gr32 = LEA64_32r killed %6:gr64, 1, killed %7:gr64_nosp, 0, $noreg

Differential Revision: https://reviews.llvm.org/D110335

Differential Revision: https://reviews.llvm.org/D110565

http://45.33.8.238/win/46013/summary.html

Preparation for D108194.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D110386

This bug was introduced by D109953. The operand order of generated FMA
is wrong.

Differential Revision: https://reviews.llvm.org/D110606

This was broken by the switch from JITTargetAddress to ExecutorAddr in
21a06254.

Reviewed By: Craig Topper, Wang Pengfei

Differential Revision: https://reviews.llvm.org/D110467

Need a more general CHECK line for testcase in 5df9112c for correctly
handling  lld-x86_64-win buildbot.

This reverts commit 94ea3664.

Reverting due to errors on buildbots.

This relands commit 16a62d4f.
Relanded after fixing CHECK-LINES for opt pipeline output to be more
general (based on failures seen in buildbot).

Slab allocator failures will now report requested size and remaining capacity.

This patch adds the following built-ins:

__builtin_vsx_build_pair
__builtin_mma_build_acc

Reviewed By: #powerpc, nemanjai, lei

Differential Revision: https://reviews.llvm.org/D107647

Part of the ongoing move to ExecutorAddr.

SplitBlockPredecessors is unable to insert an additional BasicBlock
between an indirectbr/callbr terminator and the successor blocks.
This is needed by Polly to normalize the control flow before emitting
its optimzed code.

This patches rejects regions entered by an indirectbr/callbr to not fail
later at code generation.

This fixes llvm.org/PR51964

Recommit with "REQUIRES: asserts" in test that uses statistics.

There is some use of `enable_if<...>::type` when the rest of the file
uses `enable_if_t`. So, use `enable_if_t` consistently throughout.

This reverts commit 91f46bb7 which
causes test failures when assertions are off.

This allows these error values to remain valid, even if they tear down the JIT
itself.

With improved analysis in determining CFG equivalence that does
not require strict dominance and post-dominance conditions, we
now relax  isSafeToMoveBefore() such that an instruction I can
be moved before InsertPoint even if they do not strictly dominate
each other, as long as they follow the same control flow path.

For example,  we can move Instruction 0 before Instruction 1,
and vice versa.

```
if (cond1)
   // Instruction 0: %add = add i32 1, 2
if (cond1)
   // Instruction 1: %add2 = add i32 2, 1
```

Reviewed By: Whitney

Differential Revision: https://reviews.llvm.org/D110456

This reverts commit b72176b9.

Broke bot: https://lab.llvm.org/buildbot/#/builders/70/builds/12193

The MSP430 ABI supports build attributes for specifying
the ISA, code model, data model and enum size in ELF object files.

Differential Revision: https://reviews.llvm.org/D107969