Based on https://github.com/llvm/llvm-project/pull/70766 I think it
would be good to have a few more offloading reduction tests, so we do
not accidentally break minimum and maximum reductions another time.

Move SIPreAllocateWWMRegs pass to just before VGPR allocation. This
saves recomputation of the virtual matrix and live reg map, with the
slight regression in O0 that live intervals and slot indexes must be
computed.

I'd like to be able to install just the Python core sources (without
building/including the pybind sources).

Reverts llvm/llvm-project#71054

ReassociatePass may clear nsw/nuw flags of some instructions, which may
have side effects on optimizations in IndVarSimplifyPass.

This reverts commit eab828d4.

Make it easier to control which optimizations are enabled by making
OptimizeArgs a bit masked enum. There's currently only one such
optimization, but more will be added in followup commits.

Summary:
This is a quick hack to disable affected GPU math tests so the bots will
be green again.

The offending commit is d2361b20. If
that is reverted along with this patch the tests also pass.

This caused assert:
llvm/llvm/lib/CodeGen/AsmPrinter/DwarfFile.cpp:110:
void llvm::DwarfFile::addScopeVariable(LexicalScope *, DbgVariable *):
Assertion `Ret.second' failed.

See comments https://reviews.llvm.org/D144006#4656350.

This reverts commit 3b449bd4.

This is a support for " #pragma omp atomic compare fail ". It has Parser & AST support for now.

Reviewed By: tianshilei1992, ABataev

Differential Revision: https://reviews.llvm.org/D123235

General distribution of masked writes requires materializing the permutation on the vector of the write in IR to ensure the vector lines up with the mask. For now just support cases with trivial permutation maps.

This change fixes #71518, which compared the KnownMinValue of the
scalable virtual register with the FixedSize of the physical register in
the wrong direction. It turns out that we cannot include this check at all since
it will lead to a false failures. Test cases are added to show that
the false failures no longer occur after this fix.

The check introduced in #71444 was to restrictive and this patch relax
it so data clause can accept constant.

Move options check from emitBinary to more proper
adjustCommandLineOptions.

instrumentation->hugify

Use `CreateZExtOrTrunc`, reduce test and regenerate checks.

This reverts commit cc9ad727 since it
breaks some tests upstream:

https://lab.llvm.org/buildbot/#/builders/68/builds/63112

********************
Failed Tests (4):
  lldb-api :: functionalities/gdb_remote_client/TestThreadSelectionBug.py
  lldb-api :: functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py
  lldb-api :: functionalities/plugins/python_os_plugin/stepping_plugin_threads/TestOSPluginStepping.py
  lldb-api :: functionalities/postmortem/mach-core/TestMachCore.py

When the Powers That Be decided that the name "sparse compiler" should
be changed to "sparsifier", we negected to change some of the comments
in the code; this pull request completes the name change.

This patch enforces that every scripted object implements all the
necessary abstract methods.

Every scripted affordance language interface can implement a list of
abstract methods name that checked when the object is instanciated.

Since some scripting affordances implementations can be derived from
template base classes, we can't check the object dictionary since it
will contain the definition of the base class, so instead, this checks
the scripting class dictionary.

Previously, for the various python interfaces, we used
`ABC.abstractmethod` decorators but this is too language specific and
doesn't work for scripting affordances that are not derived from
template base classes (i.e OperatingSystem, ScriptedThreadPlan, ...), so
this patch provides generic/language-agnostic checks for every scripted
affordance.

Signed-off-by: Med Ismail Bennani <ismail@bennani.ma>

vectorLength operand was counted twice - should only be counted once.

…gSizeInBits

This patch changes getRegSizeInBits to return a TypeSize instead of an
unsigned in the case that a virtual register has a scalable LLT. In the
case that register is physical, a Fixed TypeSize is returned.

The MachineVerifier pass is updated to allow copies between fixed and
scalable operands as long as the Src size will fit into the Dest size.

This is a precommit which will be stacked on by a change to GISel to
generate COPYs with a scalable destination but a fixed size source.

This patch is stacked on https://github.com/llvm/llvm-project/pull/70893
for the ability to use scalable vector types in MIR tests.

It was an unfortunate oversight from my side to forget to include this comment into the PR.

BreakpointResolver::CreateFromStructuredData returns a
BreakpointResolverSP, but all of the subclasses return raw pointers.
Instead of creating a raw pointer and shoving it into a shared pointer,
it seems reasonable to just create the shared pointer directly.

The test for atanf used <initializer_list> to simplify iterating through
an array. This caused issues with the new features.h change by creating
a
libcpp dependency in the test. This change moves the list to an array
variable, removing the need for that dependency.

The previous paragraph actually is the current definition
of the mask semantics.

Support for ELF::R_ARM_THM_MOVW_ABS_NC and ELF::R_ARM_THM_MOVT_ABS
was present but lacked tests. Test cases are similar to the ARM
versions of the relocations in ELF_static_arm_reloc.s.

This patch makes the various Scripted Interface base class abstract by
making the `CreatePluginObject` method pure virtual.

This means that we cannot construct a Scripted Interface base class
instance, so this patch also updates the various
`ScriptedInterpreter::CreateScripted*Interface` methods to return a
`nullptr` instead.`

This patch also removes the `ScriptedPlatformInterface` member from the
`ScriptInterpreter` class since it the interpreter can be owned by the
`ScriptedPlatform` instance itself, like we do for `ScriptedProcess`
objects.

Signed-off-by: Med Ismail Bennani <ismail@bennani.ma>

These have been removed in 7b9d73c2.
This is a followup patch to apply the changes to lldb.

Opaque ptr cleanup effort (NFC).

Theses functions were added in fd1e5aa8
without a declaration.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D154765

This PR adds "value casting", i.e., a mechanism to wrap `ir.Value` in a
proxy class that overloads dunders such as `__add__`, `__sub__`, and
`__mul__` for fun and great profit.

This is thematically similar to
https://github.com/llvm/llvm-project/commit/bfb1ba752655bf09b35c486f6cc9817dbedfb1bb
and
https://github.com/llvm/llvm-project/commit/9566ee280607d91fa2e5eca730a6765ac84dfd0f.
The example in the test demonstrates the value of the feature (no pun
intended):

```python
    @register_value_caster(F16Type.static_typeid)
    @register_value_caster(F32Type.static_typeid)
    @register_value_caster(F64Type.static_typeid)
    @register_value_caster(IntegerType.static_typeid)
    class ArithValue(Value):
        __add__ = partialmethod(_binary_op, op="add")
        __sub__ = partialmethod(_binary_op, op="sub")
        __mul__ = partialmethod(_binary_op, op="mul")

    a = arith.constant(value=FloatAttr.get(f16_t, 42.42))
    b = a + a
    # CHECK: ArithValue(%0 = arith.addf %cst, %cst : f16)
    print(b)

    a = arith.constant(value=FloatAttr.get(f32_t, 42.42))
    b = a - a
    # CHECK: ArithValue(%1 = arith.subf %cst_0, %cst_0 : f32)
    print(b)

    a = arith.constant(value=FloatAttr.get(f64_t, 42.42))
    b = a * a
    # CHECK: ArithValue(%2 = arith.mulf %cst_1, %cst_1 : f64)
    print(b)
```

**EDIT**: this now goes through the bindings and thus supports automatic
casting of `OpResult` (including as an element of `OpResultList`),
`BlockArgument` (including as an element of `BlockArgumentList`), as
well as `Value`.

This PR adds the processor definition for XiangShan-NanHu, an
open-source high-performance RISC-V processor.

According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/),
NanHu core supports
`RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval`.
I found that NanHu also supports `zicbom` and `zicboz`. You can find
them in the [source
code](https://github.com/OpenXiangShan/XiangShan/blob/5931ace35325a644a12f8ea27830a2de7489e7e7/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L426-L436

).
Features supported by NanHu have been confirmed by @poemonsense.

---------

Co-authored-by: SForeKeeper <zkliu6@gmail.com>