1. Feb 02, 2022
  2. Feb 01, 2022
    • Mircea Trofin's avatar
      [nfc][regalloc] Move DefaultEvictionAdvisor::* to RegAllocEvictionAdvisor.cpp · 22d3bbdf
      Mircea Trofin authored
      This is leftover from the advisor refactoring. Straight-forward copy and
      paste.
      22d3bbdf
    • Craig Topper's avatar
      [RISCC] Add missing words to comment. NFC · f943c58c
      Craig Topper authored
      f943c58c
    • Craig Topper's avatar
      [RISCV] Fix a vsetvli insertion bug involving loads/stores. · 7eb78107
      Craig Topper authored
      The first phase of the analysis can avoid a vsetvli if an earlier
      instruction in the block used an SEW and LMUL that when combined with
      the EEW of the load/store would produce the desired EMUL. If we
      avoided a vsetvli this will affect the global analysis we do in the
      second phase.
      
      The third phase where we really insert the vsetvlis needs to agree
      with the first phase. If it doesn't we can insert vsetvlis that
      invalidate the global analysis.
      
      In the test case there is a VSETVLI in the preheader that sets
      SEW=64 and LMUL=1. Inside the loop there is a VADD with SEW=64 and LMUL=1.
      This VADD is followed by a store that wants wants SEW=32 LMUL=1/2.
      Because it has EEW=32 as part of the opcode the SEW=64 LMUL=1 from the
      VADD can be become EMUL=1 for the store. So the first phase determines no
      vsetvli is needed.
      
      The third phase manages CurInfo differently than BBInfo.Change from the
      first phase. CurInfo is only updated when we see a vsetvli or insert
      a vsetvli. This was done to allow predecessor block information from
      the global analysis to be applied to multiple instructions. Since the
      loop body has no vsetvli we won't update CurInfo for either the VADD
      or the VSE. This prevented us from checking the store vsetvli elision
      for the VSE resulting in a vsetvli SEW=32 LMUL=1/2 being emitted which
      invalidated the global analysis.
      
      To mitigate this, I've added a BBLocalInfo variable that more closely
      matches the first phase propagation. This gets updated based on the
      VADD and prevents emitting a vsetvli for the store like we did in the
      first phase.
      
      I wonder if we should do an earlier phase to handle the load/store case
      by adding more pseudo opcodes and changing the SEW/LMUL for those
      instructions before the insertion analysis. That might be more robust
      than trying to guarantee two phases make the same decision.
      
      Fixes the test from D118629.
      
      Reviewed By: frasercrmck
      
      Differential Revision: https://reviews.llvm.org/D118667
      7eb78107
    • Stanislav Gatev's avatar
      [clang][dataflow] Enable comparison of distinct values in Environment · 6b8800df
      Stanislav Gatev authored
      Make specializations of `DataflowAnalysis` extendable with domain-specific
      logic for comparing distinct values when comparing environments.
      
      This includes a breaking change to the `runDataflowAnalysis` interface
      as the return type is now `llvm::Expected<...>`.
      
      This is part of the implementation of the dataflow analysis framework.
      See "[RFC] A dataflow analysis framework for Clang AST" on cfe-dev.
      
      Reviewed-by: ymandel, xazax.hun
      
      Differential Revision: https://reviews.llvm.org/D118596
      6b8800df
    • Craig Topper's avatar
      [RISCV] Don't make it an error have Zve* and V at the same time. · 2f023b94
      Craig Topper authored
      This should not be an error. V is a valid implementation of Zve.
      
      Spec clarified here
      https://github.com/riscv/riscv-v-spec/commit/9a877e8553362ff03a9b22b98e321b59aff50398
      
      Differential Revision: https://reviews.llvm.org/D118679
      2f023b94
    • Sam McCall's avatar
      7af1a2ed