Summary: This adds a customization point to support unpoisoning of signal alternate stacks on POSIX.

Reviewers: vitalybuka

Reviewed By: vitalybuka

Subscribers: #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D81577

Note that .eh_frame sections are generated in the 32-bit format even
when debug sections are 64-bit, for compatibility reasons. They use
relative references between entries, so they hardly benefit from the
64-bit format.

Differential Revision: https://reviews.llvm.org/D81149

DW_FORM_sec_offset was introduced in DWARFv4, so, for 64-bit DWARFv3,
DW_FORM_data8 should be used instead.

Differential Revision: https://reviews.llvm.org/D81148

In addition, the patch fixes referencing the section within
a compilation unit.

Differential Revision: https://reviews.llvm.org/D81147

Differential Revision: https://reviews.llvm.org/D81146

The patch enables producing DWARF64 compilation units and fixes
generating references to .debug_abbrev and .debug_line sections.
A similar change for .debug_ranges/.debug_rnglists will be added
in a forthcoming patch.

Differential Revision: https://reviews.llvm.org/D81145

Differential Revision: https://reviews.llvm.org/D81144

The patch adds an option `--dwarf64` to instruct a tool to generate
debug information in the 64-bit DWARF format. There is no real
implementation yet, only a few compatibility checks.

Differential Revision: https://reviews.llvm.org/D81143

This patch extends MatchVectorAllZeroTest to handle OR vector reduction patterns where the result is compared against zero.

Fixes PR45378

Differential Revision: https://reviews.llvm.org/D81547

[X86][SSE] combineVectorSizedSetCCEquality - move single Subtarget.hasAVX() use into condition. NFC.

We already have Subtarget.hasSSE2() and Subtarget.useAVX512Regs() in the condition - seems to be a legacy from when we had multiple uses.

Fix memref region compute for 0-d memref accesses in certain cases (when
there are loops surrounding such 0-d accesses).

Differential Revision: https://reviews.llvm.org/D81792

Have TTI::getInstructionThroughput call getUserCost for Br, Ret and
PHI. This now means that eveything in getInstructionThroughput is
handled by getUserCost.

Differential Revision: https://reviews.llvm.org/D79849

The variable was not used anywhere except assert and causes build
warnings in the optimized builds.

Clanup after 913bc312

The grouping now reflects the grouping on cppreference.com.

Add the following canonicalization
- and(x, 1) -> x
- subi(x, 0) -> x

Differential Revision: https://reviews.llvm.org/D81534

- Modify HasParent trait to allow one of several op's as a parent -
- Expose this trait in the ODS framework using the ParentOneOf<> trait.

Differential Revision: https://reviews.llvm.org/D81880

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D81814

Note: don't do this for integer 64 bit materialization to match SDAG.

Differential Revision: https://reviews.llvm.org/D81893

Only functions with floating-point return type accepts fast-math flags.
When adding such flags to function returning integer, we'll see a crash,
because there's still an undeleted value referencing the argument. This
patch manually removes the temporary instruction when error occurs.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D78355

This patch implements the .debug_addr section.

Reviewed By: jhenderson, grimar

Differential Revision: https://reviews.llvm.org/D81541

Summary: Also fixed the InlineAdvisor.cpp license.

Reviewers: rriddle

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81896

Limiting to x86-64 since that's when __int128 is legal in clang.

Differential Revision: https://reviews.llvm.org/D81817

This diff adds support for copying binaries
containing a LC_CODE_SIGNATURE load command.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D81768

This patch is a follow up on https://reviews.llvm.org/D81627.

In addition to default -fno-gpu-rdc case, this patches let
HIP toolchain not use llvm-link/opt/llc to link device code
for -fgpu-rdc case. Instead, uses standard lto.

This will eliminate some redundant optimizations and speed
up the compilation/linking.

Differential Revision: https://reviews.llvm.org/D81861

Summary:
Normally, the Origin is passed over TLS, which seems like it introduces unnecessary overhead. It's in the (extremely) cold path though, so the only overhead is in code size.

But with eager-checks, calls to __msan_warning functions are extremely common, so this becomes a useful optimization.

This can save ~5% code size.

Reviewers: eugenis, vitalybuka

Reviewed By: eugenis, vitalybuka

Subscribers: hiraditya, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D81700

Fixes UBSAN error after rG9ee272f1
A trivial signed/unsigned shift.

which takes an address and a length and returns all lines within that
address range.

MSVC uses lit for STL testing to run both the libcxx tests and our "native" suite of tests which has feature requirements that are not parsed from the test content. For consistency, the change treats the `unsupported` and `xfails` `Test` properties similarly to `requires`.

Differential Revision: https://reviews.llvm.org/D81782

Add two more perf monitors to MachTask::GetProfileData.

<rdar://problem/63984105>

It's possible to end up with a zext or something in the way of a G_CONSTANT,
even pre-legalization. This can happen with memsets.

e.g.

https://godbolt.org/z/Bjc8cw

To make sure we can catch these cases, use `getConstantVRegValWithLookThrough`
instead of `mi_match`.

Differential Revision: https://reviews.llvm.org/D81875