When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc
have the same type (creates COPY) use Src register directly or
use replaceRegOrBuildCopy instead.

Differential Revision: https://reviews.llvm.org/D108306

Differential Revision: https://reviews.llvm.org/D108204

In streaming mode on SME targets only the scalar BFCVT armv8.6-a
instruction is legal, predicate the illegal instructions on NEON to
disable them in streaming mode (see D107902). BFCVT is predicated on
HasNEONorStreamingSVE.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06/SIMD-FP-Instructions

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D108279

With LLVM_LINK_LLVM_DYLIB and LLVM_POLLY_LINK_INTO_TOOLS, Polly is
already linked into libLLVM.so, linking libPolly.a as well into
unittests results in duplicate command line registration errors.

This does the same as D96259, but for ARM, just like AArch64,
using the same comment char as for ELF and MinGW mode.

As the assembly input/output of LLVM is GAS style, trying to
match what MS armasm.exe does isn't needed (because the comment
char used is the least concern when it comes to that; all
directives differ too). If a separate armasm compatible mode
is implemented, it can use its own comment style (just like
llvm-ml implements MS ml.exe compatible assembly parsing).

This fixes building compiler-rt assembly files for ARM in MSVC
mode.

The updated testcase literals-comments.s was only intended to
make sure that '#' isn't interpreted as a comment char.

Differential Revision: https://reviews.llvm.org/D107251

With uses of g_atl_machine gone, a significant portion of dead
code has been removed.

This patch depends on D104691 and D104695.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D104696

In commit 9bb33f57, a pair of superfluous braces are introduced to the function Sema::BuildDeclarationNameExpr.
This patch tries to remove the superfluous braces. Also use clang-format to further beautify the above function.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D108609

Add `ashr` instruction to the DAG post-dominated by `trunc`, allowing
`TruncInstCombine` to reduce bitwidth of expressions containing
these instructions.

We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are sign bits (all zeros or ones) and
one sign bit is left untruncated: https://alive2.llvm.org/ce/z/Ajo2__

Part of https://reviews.llvm.org/D107766

Differential Revision: https://reviews.llvm.org/D108355

WrapperFunctionResult no longer supports wrapping constant data, so this patch
provides direct non-const access to the wrapped data. Since wrapped data can now
be written, the WrapperFunctionResult::allocate method can be simplified to
return a WrapperFunctionResult.

This is essentially the same change (and with the same motivation) as LLVM
commit 8b117830, but applied to the ORC runtime's WrapperFunctionResult code.

Add `sext` for `ashr`, remove unrelated tests

WrapperFunctionResult no longer supports wrapping constant data, so this patch
adds a non-const data method. Since data can now be written through the data
method, the allocate method can be simplified to return a WrapperFunctionResult.

This patch enables basic complex functionality using the ocml builtins.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D108552

Fix assertion fail when building con constant vector which element type is half.

Differential Revision: https://reviews.llvm.org/D108612

This patch handles the up and down keys if they weren't handled by the
selected field. Moreover, it makes sure the form always absorb the key
to take full control until the form is canceled or submitted.

Differential Revision: https://reviews.llvm.org/D108414

The last use was removed on Jun 9, 2015 in commit
d9699bc7.

This patch adds a new key ALt+Enter key combination to form windows.
Once invoked, the first action is executed without having to navigate to
its button.

Field exit callbacks are now also invoked on validation to support this
aforementioned key combination.

One concern for this key combination is its potential use by the window
manager of the host. I am not sure if this will be a problem, but it is
worth putting in consideration.

Differential Revision: https://reviews.llvm.org/D108410

In the raw profile, binary ids immediately follow the header so when
computing counters offset we need to account for the new section.

Differential Revision: https://reviews.llvm.org/D108608

This patch adds many new keys to the text field and implements new
behaviors as follows:

```
case KEY_HOME:
case KEY_CTRL_A:
  MoveCursorToStart();
case KEY_END:
case KEY_CTRL_E:
  MoveCursorToEnd();
case KEY_RIGHT:
case KEY_SF:
  MoveCursorRight();
case KEY_LEFT:
case KEY_SR:
  MoveCursorLeft();
case KEY_BACKSPACE:
case KEY_DELETE:
  RemovePreviousChar();
case KEY_DC:
  RemoveNextChar();
case KEY_EOL:
case KEY_CTRL_K:
  ClearToEnd();
case KEY_DL:
case KEY_CLEAR:
  Clear();
```

This patch also refactors scrolling to be dynamic at draw time for
easier handing.

Differential Revision: https://reviews.llvm.org/D108385

Enable FP16 FMA instructions.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105268

This is pretty similar to the ST2 selection code in
`AArch64InstructionSelector::selectIntrinsicWithSideEffects`.

This is a GISel equivalent of the ld2 case in `AArch64DAGToDAGISel::Select`.
There's some weirdness there that appears here too (e.g. using ld1 for scalar
cases, which are 1-element vectors in SDAG.)

It's a little gross that we have to create the copy and then select it right
after, but I think we'd need to refactor the existing copy selection code
quite a bit to do better.

This was falling back while building llvm-project with GISel for AArch64.

Differential Revision: https://reviews.llvm.org/D108590

This change adds the option --resultdb-output=path allow llvm-lit
generating LuCI ResultDB JSON output for the test results, which
can be better integrated with certain CI/CQ framework.

Differential Revision: https://reviews.llvm.org/D108238

Differential Revision: https://reviews.llvm.org/D108565

Fixes https://bugs.llvm.org/show_bug.cgi?id=51414.

Differential Revision: https://reviews.llvm.org/D108021

DWARFDie::getDeclFile(...) previously only supported getting the DW_AT_decl_file if the DIE itself contained the DW_AT_decl_file attribute, or if the DIE had a DW_AT_abstract_origin that pointed to another DIE that had a DW_AT_decl_file. This patch allows the function to get the right attribute value if there is a DW_AT_specification that points to another DIE. We also test that if a DW_AT_abtract_origin or DW_AT_specification points to a DIE in another CU with a DW_FORM_ref_addr, that the right line table is used to extract the file index.

Full tests were added for the following cases:
- DIE has a DW_AT_decl_file attribute
- DIE has a DW_AT_abtract_origin that points to another die in the same CU
- DIE has a DW_AT_abtract_origin that points to another die in another CU
- DIE has a DW_AT_specification that points to another die in the same CU
- DIE has a DW_AT_specification that points to another die in another CU

Differential Revision: https://reviews.llvm.org/D108480

Compiled nvptx devicertl as freestanding, breaking the
dependency on host glibc and gcc-multilibs. Thus build it by default.

Comes at the cost of #defining out printf. Tried mapping it onto
__builtin_printf but that gets transformed back to printf instead
of hitting the cuda/openmp lowering transform.

Printf could be preserved by one of:
- dropping all the standard headers and ffreestanding
- providing a header only printf implementation
- changing the compiler handling of printf

Reviewed By: grokos

Differential Revision: https://reviews.llvm.org/D108349

When using final reward (which is now the default), we were skipping
logging decisions that were leading to callee deletion. This fixes that.

Differential Revision: https://reviews.llvm.org/D108587

This was already the case, but the recent change (95733438) altered
the behavior on some of our bots where __unw_add_dynamic_fde is not
found. This restores the prior behavior on Darwin while also retaining
the new behavior from that change.

Rationale:
Passing in a pointer to the memref data in order to implement the
dense to sparse conversion was a bit too low-level. This revision
improves upon that approach with a cleaner solution of generating
a loop nest in MLIR code itself that prepares the COO object before
passing it to our "swiss army knife" setup.  This is much more
intuitive *and* now also allows for dynamic shapes.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D108491

Adds atoi, atol, atoll, strtol, strtoll, strtoul, and strtoull to the
list of entrypoints for Windows and aarch64 linux, as well as moving
them out of the LLVM_LIBC_FULL_BUILD condition for x86_64 linux.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D108477

This is a re-try of 3aa009cc which was reverted at
9577fac0 because it caused an infinite loop.

For the extra test case, either re-ordering the transforms
or adding the extra clause to avoid sub-of-sub is enough
to prevent the infinite compile, but I'm doing both to be
safer.

Original commit message:
The motivation was to get min/max intrinsics to parity
with cmp+select idioms, but this unlocks a few more
folds because isFreeToInvert recognizes add/sub with
constants too.

In the min/max example, we have too many extra uses
for smaller folds to improve things, but this fold
is able to eliminate uses even though we can't reduce
the number of instructions.

[TargetMachine] Move COFF special case for ExternalSymbolSDNode from shouldAssumeDSOLocal to X86Subtarget

Intended to be NFC. ARM/AArch64 don't appear to need adjustment.

TargetMachine::shouldAssumeDSOLocal is expected to be very simple, ideally
matching isDSOLocal(). The IR producers are expected to set dso_local correctly.
(While some may think this function can make producers' work easier, the
function is really not in a good position to set dso_local. See the various
special cases we duplicate from clang CodeGenModule.cpp.)

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D108514

This revision adds native ODS support for VariadicOfVariadic operand
groups. An example of this is the SwitchOp, which has a variadic number
of nested operand ranges for each of the case statements, where the
number of case statements is variadic. Builtin ODS support allows for
generating proper accessors for the nested operand ranges, builder
support, and declarative format support. VariadicOfVariadic operands
are supported by providing a segment attribute to use to store the
operand groups, mapping similarly to the AttrSizedOperand trait
(but with a user defined attribute name).

`build` methods for VariadicOfVariadic operand expect inputs of the
form `ArrayRef<ValueRange>`. Accessors for the variadic ranges
return a new `OperandRangeRange` type, which represents a
contiguous range of `OperandRange`. In the declarative assembly
format, VariadicOfVariadic operands and types are by default
formatted as a comma delimited list of value lists:
`(<value>, <value>), (), (<value>)`.

Differential Revision: https://reviews.llvm.org/D107774

This should reduce the amount of noise issued by clang for the recent-ish CUDA
versions.

Clang still does not support all the features offered by NVCC, but is expected
to handle CUDA headers and produce binaries for all GPUs supported by NVCC.

Differential Revision: https://reviews.llvm.org/D108248

Always use cuda.h to detect CUDA version. It's a more universal approach
compared to version.txt which is no longer present in recent CUDA versions.

Split the 'unknown CUDA version' warning in two:

* when detected CUDA version is partially supported by clang. It's expected to
work in general, at the feature parity with the latest supported CUDA
version. and may be missing support for the new features/instructions/GPU
variants. Clang will issue a warning.

* when detected version is new. Recent CUDA versions have been working with
clang reasonably well, and will likely to work similarly to the partially
supported ones above. Or it may not work at all. Clang will issue a warning and
proceed as if the latest known CUDA version was detected.

Differential Revision: https://reviews.llvm.org/D108247

Differential Revision: https://reviews.llvm.org/D108239

It's the oldest GPU architecture currently supported by all CUDA versions clang
can use.

Differential Revision: https://reviews.llvm.org/D108235

Revert rG1c9bec72 : [InstCombine] Fold (gep (oneuse(gep Ptr, Idx0)), Idx1) -> (gep Ptr, (add Idx0, Idx1)) (PR51069)

Reverted (manually due to merge conflicts) while regressions reported on PR51540 are investigated

As noticed on D106352, after we've folded "(select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0))" if the inner Ptr was also a (now one use) gep we could then merge the geps, using the sum of the indices instead.

I've limited this to basic 2-op geps - a more general case further down InstCombinerImpl.visitGetElementPtrInst doesn't have the one-use limitation but only creates the add if it can be created via SimplifyAddInst.

https://alive2.llvm.org/ce/z/f8pLfD (Thanks Roman!)

Differential Revision: https://reviews.llvm.org/D106450

It appears that the Read operand for stores was being placed on the
first operand (the stored value) not the address base. This adds a
ReadST for the stored value operand, allowing the ReadAdrBase to
correctly act upon the address.

Differential Revision: https://reviews.llvm.org/D108287