Test coverage for an upcoming change, we can avoid generating an immediate
in register if we know the immediate is equal to vlmax.

This will help catch any regressions introduced in the main branch
before we start release testing.

For vectors with either leading or trailing unit dim, replaces:

    elementwise(a, b)

with:

    sc_a = shape_cast(a)
    sc_b = shape_cast(b)
    res = elementwise(sc_a, sc_b)
    return shape_cast(res)

The newly inserted shape_cast Ops fold (before elementwise Op) and then
restore (after elementwise Op) the unit dim. Vectors `a` and `b` are
required to be rank > 1.

Example:
```mlir
  %mul = arith.mulf %B_row, %A_row : vector<1x[4]xf32>
  %cast = vector.shape_cast %mul : vector<1x[4]xf32> to vector<[4]xf32>
```

gets converted to:

```mlir
  %B_row_sc = vector.shape_cast %B_row : vector<1x[4]xf32> to vector<[4]xf32>
  %A_row_sc = vector.shape_cast %A_row : vector<1x[4]xf32> to vector<[4]xf32>
  %mul = arith.mulf %B_row_sc, %A_row_sc : vector<[4]xf32>
  %mul_sc = vector.shape_cast %mul : vector<[4]xf32> to vector<1x[4]xf32>
  %cast = vector.shape_cast %mul_sc : vector<1x[4]xf32> to vector<[4]xf32>...

Fixes #74876.

During the parsing of `operator<(Foo&) {}`, there was no handling for
the operator<, so it called `consumeToken()` again, causing the
`AnnotationParser::Scopes` to have one additional left brace each time
it tried to parse it, leaving it unbalanced.
Because of this, in the following code:
```cpp
class Foo {
  void operator<(Foo&) {}
  Foo& f;
};
```
The `&` in the reference member, was being interpreted as
`TT_BinaryOperator` instead of `TT_PointerOrReference`.

Re-apply 7f215b13, which was reverted in
a9e3d232.

The orginal commit uncovered a bug that was fixed by
4701f776.

Fixes #58680

This simplifies handling tags by user code. Now code does not need
to know bit size of tag and its position.

Because it does not implemented pthread_barrier_t.

* Fix `take_view::__sentinel`'s `operator==`
* Rename `ranges/range.adaptors/range.take/sentinel/base.pass.cpp`
directory to
`ranges/range.adaptors/range.take/range.take.sentinel/base.pass.cpp`
* Add ***full*** test coverage for `take_view::__sentinel`'s
`operator==`
* Drive-by: fix comment in `base.pass.cpp` test
* Close #55211

When we use the -nostdlib++ flag, we don't need to explicitly link
against compiler-rt, since the compiler already links against it by
default. This simplifies the flags that we need to use when building
with Clang and GCC, and opens the door to further simplifications since
most platforms won't need to detect whether libgcc and libgcc_s are
supported anymore.

Furthermore, on platforms where -nostdlib++ is used, this patch prevents
manually linking compiler-rt *before* other system libraries. For
example, Apple platforms have several compiler-rt symbols defined in
libSystem.dylib. If we manually link against compiler-rt, we end up
overriding the default link order preferred by the compiler and
potentially using the symbols from the clang-provided libclang_rt.a
library instead of the system provided one.

Note that we don't touch how libunwind links against compiler-rt when it
builds the .so/.a because li...

Branch-absolute instructions are currently printed in decimal, and
negative addresses are printed as positive numbers.

With this change, addresses are printed in hex and negative addresses
are converted to an unsigned 32- or 64-bit address.

BUFFER_LOAD_DWORD_LDS was incorrectly touching vscnt instead of the
vmcnt. This is VMEM load and DS store, so it shall use vmcnt.

This adds support for UNIX socket communication to work similarly to
raw_stream.

---------

Patch by Christian Riis

__has_feature(builtin_headers_in_system_modules) was added in
https://reviews.llvm.org/D159483 to be used in the stdarg/stddef
implementation headers. It ended up being unnecessary, but I forgot to
remove the feature definition.

The test:
```
  module mmm
    real rrr
    namelist /aaa/ rrr
  end

    use mmm, bbb => aaa
    rrr = 3.
    write(*,bbb)
  end
```
Should output:  &AAA RRR= 3./

not:            &BBB RRR= 3./

This patch adds strnlen to the zOSSupport.h file to fix build failures in multiple files.

Fixes #75261

Follow up to #72727. The added test could not be executed on Android.

Middle end up optimizations can speculate away the short circuit
behavior of C/C++ && and ||. Using i1 and/or or logical select
instructions and a single branch.

SelectionDAGBuilder can turn i1 and/or/select back into multiple
branches, but this is disabled when jump is expensive.

RISC-V can use slt(u)(i) to evaluate a condition into any GPR which
makes us better than other targets that use a flag register. RISC-V also
has single instruction compare and branch. So its not clear from a code
size perspective that using compare+and/or is better.

If the full condition is dependent on multiple loads, using a logic
delays the branch resolution until all the loads are resolved even if
there is a cheap condition that makes the loads unnecessary.

PowerPC and Lanai are the only CPU targets that use setJumpIsExpensive.
NVPTX and AMDGPU also use it but they are GPU targets. PowerPC appears
to have a MachineIR pass that turns AND/OR of CR bits into multiple
branches. I don't know anything about Lanai and their reason for using
setJumpIsExpensive.

I think the decision to use logic vs branches is much more nuanced than
this big hammer. So I propose to make RISC-V match other CPU targets.

Anyone who wants the old behavior can still pass -mllvm
-jump-is-expensive=true.

Code generation can sometimes simplify expensive operations when
an operand is constant.  An example of this is divides on AArch64
where they can be rewritten using a cheaper sequence of multiplies
and subtracts.  Doing this is often better than hoisting expensive
constants which are likely to be hoisted by MachineLICM anyway.

This commit fixes a bug where identifiers were not swapped when doing a
IntegerRelation::swapVar.

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.

When building with compiler-rt enabled, warnings such as the following
are
observed:


llvm-project/llvm/build/projects/compiler-rt/../libc/include/llvm-libc-macros/linux/sys-stat-macros.h:46:9:
    warning: 'S_IXOTH' macro redefined [-Wmacro-redefined]
    #define S_IXOTH 00001
            ^

llvm-project/llvm/build/projects/compiler-rt/../libc/include/llvm-libc-macros/linux/fcntl-macros.h:61:9:
    note: previous definition is here
    #define S_IXOTH 01
            ^
It looks like we have these multiply defined. Deduplicate these flags;
users
should expect to find them in sys/stat.h. S_FIFO was wrong anyways
(should
have been S_IFIFO).

The flag -fms-volatile has existed as a -cc1 flag for a while. It also
technically existed as a driver flag, but didn't do anything because it
wasn't wired up to anything in the driver.

This patch adds -fno-ms-volatile, and makes both -fms-volatile and
-fno-ms-volatile work the same way as the cl-mode flags. The defaults
are unchanged (default on for x86 in cl mode, default off otherwise).

This patch fixes:

  llvm/lib/Transforms/Scalar/ConstraintElimination.cpp:1112:13: error:
  unused function 'dumpUnpackedICmp' [-Werror,-Wunused-function]

This patch implements the builtins in Clang
and the LLVM-IR intrinsic for the following:

// Variants are also available for:
// _s8, _s16, _u16, _s32, _u32, _s64, _u64,
// _f16, _f32, _f64uint8x16_t svaddqv[_u8](svbool_t pg, svuint8_t zn);

// Variants are also available for:
// _s8, _u16, _s16, _u32, _s32, _u64, _s64
uint8x16_t svandqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t
sveorqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t svorqv[_u8](svbool_t
pg, svuint8_t zn);

// Variants are also available for:
// _s8, _u16, _s16, _u32, _s32, _u64, _s64;
uint8x16_t svmaxqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t
svminqv[_u8](svbool_t pg, svuint8_t zn);

// Variants are also available for _f32, _f64
float16x8_t svmaxnmqv[_f16](svbool_t pg, svfloat16_t zn); float16x8_t
svminnmqv[_f16](svbool_t pg, svfloat16_t zn);

According to the PR#257[1]

The reduction instruction uses scalable vectors as input and fixed
vectors as output, therefore we changed SVEEmitter to emit fixed vector
types in case the neon header(arm_neon.h) is not present.

[1]https://github.com/ARM-software/acle/pull/257

Co-author: Dinar Temirbulatov <dinar.temirbulatov@arm.com>

Add empty AMDGPUGlobalISelDivergenceLowering pass. This pass will
implement
- selection of divergent i1 phis as lane mask phis, requires lane mask
merging in some cases
- lower uses of divergent i1 values outside of the cycle using lane mask
merging
- lowering of all cases of temporal divergence:
- lower uses of uniform i1 values outside of the cycle using lane mask
merging
- lower uses of uniform non-i1 values outside of the cycle using a copy
to vgpr inside of the cycle

Add very detailed set of regression tests for cases mentioned above.

patch 1 from: https://github.com/llvm/llvm-project/pull/73337

This is necessary for visualization of optimization remarks.

m_Specific can only be used if the previous check suceeded. Found by
msan.

The specialization was non-conforming because it was missing a bunch of
member functions. Those were missing probably just as an oversight
coupled with a bit of laziness -- the rule that user-defined
specializations need to match the base template is usually OK to take
with a grain of salt, but not when the code is supposed to be portable,
which our test suite aims to be.

Fixes #74214

This patch refactors `checkCondition` to handle min/max intrinsic calls
in #75306.

This patch tracks li instructions that set AVL operands and does DCE
after emitting VSETVLIs.

Even though constexpr implicitly makes functions inline, we try not to
rely on this implicit effect in the code base. We are mostly consistent
about using `inline` on non-template free-functions to make it clear
that we don't have an ODR violation.

This patch simply fixes a few places where we didn't explicitly use
inline on non-template free functions, presumably because they were
constexpr.

Fixes #75227

PR 75095 introduced some changes to lld that broke some dwarf tests that
were being incorrectly linked as a PIE. Add flags to disable any PIC/PIE
compilation, so the linker can succeed and the tests can run as
intended.

This is the 1st step for D40776, to help us find missing and duplicated
tests.

As part of RemoveDIs, we need instruction insertion to be done with
iterators rather than instruction pointers, so that we can communicate
some debug-info facts about the position. This patch is an entirely
mechanical replacement of Instruction * with BasicBlock::iterator, plus
using insertBefore to insert some instructions because we don't have
iterator-taking constructors yet.

Sadly it's not NFC because it causes dbg.value intrinsics / their
DPValue equivalents to shift location.