1. May 06, 2021
  2. May 05, 2021
    • Guillaume Chatelet's avatar
      [libc] Normalize LIBC_TARGET_MACHINE · 7c2ece52
      Guillaume Chatelet authored
      Current implementation defines LIBC_TARGET_MACHINE with the use of CMAKE_SYSTEM_PROCESSOR.
      Unfortunately CMAKE_SYSTEM_PROCESSOR is OS dependent and can produce different results.
      An evidence of this is the various matchers used to detect whether the architecture is x86.
      
      This patch normalizes LIBC_TARGET_MACHINE and renames it LIBC_TARGET_ARCHITECTURE.
      I've added many architectures but we may want to limit ourselves to x86 and ARM.
      
      Differential Revision: https://reviews.llvm.org/D101524
      7c2ece52
    • Fraser Cormack's avatar
      efc31be7
    • Jessica Clarke's avatar
      [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach... · 6e876f9d
      Jessica Clarke authored
      [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics
      
      Unlike normal loads these don't have an extension field, but we know
      from TargetLowering whether these are sign-extending or zero-extending,
      and so can optimise away unnecessary extensions.
      
      This was noticed on RISC-V, where sign extensions in the calling
      convention would result in unnecessary explicit extension instructions,
      but this also fixes some Mips inefficiencies. PowerPC sees churn in the
      tests as all the zero extensions are only for promoting 32-bit to
      64-bit, but these zero extensions are still not optimised away as they
      should be, likely due to i32 being a legal type.
      
      This also simplifies the WebAssembly code somewhat, which currently
      works around the lack of target-independent combines with some ugly
      patterns that break once they're optimised away.
      
      Reviewed By: RKSimon, atanasyan
      
      Differential Revision: https://reviews.llvm.org/D101342
      6e876f9d
    • Vang Thao's avatar
      [GlobalISel] Fix buildZExtInReg creating new register. · a3d273c9
      Vang Thao authored
      Fix a bug where buildZExtInReg will create and use a new register instead of using the register from parameter DstOp Res.
      
      Reviewed By: arsenm, foad
      
      Differential Revision: https://reviews.llvm.org/D101871
      a3d273c9
    • Sanjay Patel's avatar
      [InstCombine] improve readability; NFC · 00341978
      Sanjay Patel authored
      00341978
    • Simon Pilgrim's avatar
      [MIPS][MSA] Regenerate immediates tests. NFCI. · 0f97afe3
      Simon Pilgrim authored
      Simplifies an upcoming patch diff
      0f97afe3