works both along runtime path and pure codegen path

Reviewed By: Peiming

Differential Revision: https://reviews.llvm.org/D136389

As @python3kgae pointed out we're going to want to assign these IDs
after optimization so that we can remove unused resrouces. This patch
just removes the unused ID value from the frontend metadata, clang code
generation, and updates associated test cases.

Reviewed By: python3kgae

Differential Revision: https://reviews.llvm.org/D136271

1. When we evaluating an expression multiple times and the searching scope is translation unit, ParseDeclsForContext iterates the type info and symbol info multiple times, though only the debug info is parsed once. Using llvm::call_once to make it only iterating and parsing once.

2. When evaluating an expression with identifier whose parent scope is a namespace, ParseDeclsForContext needs to search the entire type info to complete those records whose name is prefixed with the namespace's name and the entire symbol info to to parse functions and non-local variables. Caching parsed namespaces to avoid unnecessary searching.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D136006

When the common value is part of either select condition,
this is safe to reduce. Otherwise, it is not poison-safe
(with the select form of the pattern):
https://alive2.llvm.org/ce/z/FxQTzB

This is another patch motivated by issue #58313.

Let MLIR ODS also support generating build() functions without result type parameters when the op contains regions.

Regions were intentionally left unsupported: https://github.com/llvm/llvm-project/commit/398f04aa49109fd5d1eff2c1946a2956dc6b29c6

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D136232

This patch adds a lowering pass to convert `index` dialect ops to LLVM.

Depends on D135694

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D135697

This patch adds folders for `index` dialect ops. Ths folders are
careful to ensure that fold results are valid on both 32-bit and 64-bit
targets.

Depends on D135689

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D135694

This patch adds the definitions for the operations and attributes (just
one enum attribute) for the `index` dialect.

Depends on D135688

Reviewed By: rriddle, jpienaar

Differential Revision: https://reviews.llvm.org/D135689

This patch introduces the `index` dialect and associated boilerplate for
adding ops and enums (comparison predicates).

Reviewed By: rriddle, jpienaar, nicolasvasilache

Differential Revision: https://reviews.llvm.org/D135688

```
template <typename T> struct A {
  A() {}
  int value = 0;
};

template <typename Value> struct B {
  static A<int> a;
};

template <typename Value> A<int> B<Value>::a;

inline int foo() {
  return B<int>::a.value;
}
```

```
clang++ -c -fno-pic a.cc -o weak.o
g++ -c -fno-pic a.cc -o unique.o  # --enable-gnu-unique-object

# Duplicate symbol error. In postParse, we do not check `sym.binding`
ld.lld -e 0 weak.o unique.o
```

Mixing GCC and Clang object files in this case is not ideal. .bss._ZGVN1BIiE1aE
has different COMDAT groups. It appears to work in practice because the guard
variable prevents harm due to double initialization.

For the linker, we just stick with the rule that a weak binding does not cause
"duplicate symbol" errors.

Close https://github.com/llvm/llvm-project/issues/58232

Differential Revision: https://reviews.llvm.org/D136381

1) Use a static array of pointer to retain the dummy vars.
2) Associate liveness of the array with that of the runtime hook variable
   __llvm_profile_runtime.
3) Perform the runtime initialization through the runtime hook variable.
4) Preserve the runtime hook variable using the -u linker flag.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D136192

This patch adds the assembly/disassembly for the following instructions:

FDOT : Half-precision floating-point dot product
FDOT : Half-precision floating-point indexed dot product

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D136427

The `scf.index_switch` is a control-flow operation that branches to one of the
given regions based on the values of the argument and the cases. The
argument is always of type `index`.

Example:

```mlir
%0 = scf.index_switch %arg0 -> i32
case 2 {
  %1 = arith.constant 10 : i32
  scf.yield %1 : i32
}
case 5 {
  %2 = arith.constant 20 : i32
  scf.yield %2 : i32
}
default {
  %3 = arith.constant 30 : i32
  scf.yield %3 : i32
}
```

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D136003

I often run llvm-reduce on IR that contains debug info, this prevents an
extra step of `opt -passes=strip` I do every time and will result in a
lot less invalid reductions around debug metadata.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D136208

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136411

This does not appear to affect codegen, but using SGPR classes for
operands of VALU instructions looked weird.

Differential Revision: https://reviews.llvm.org/D136459

Outline the code that generates the loop structure to iterate over a dense
tensor or a sparse constant to genDenseTensorOrSparseConstantIterLoop.

Move a few routines to CodegenUtils for sharing.

Reviewed By: wrengr

Differential Revision: https://reviews.llvm.org/D136210

Verify the LiveVariables analysis after a pass that claims to preserve
it, even if there are no further passes (apart from the verifier itself)
that would use the analysis.

Differential Revision: https://reviews.llvm.org/D129213

This is obviously correct for real logic instructions,
and it also works for the poison-safe variants that use
selects:
https://alive2.llvm.org/ce/z/wyHiwX

This is motivated by the lack of 'xor' folding seen in issue #58313.
This more general fold should help reduce some of those patterns,
but I'm not sure if this specific case does anything for that
particular example.

Separating the matches makes it easier
to enhance for commutative patterns.

FIRSupports includes headers from HLFIRDialect that are generated at
compile time. Therefore it must wait until these headers have been
generated.

Fix flang bot failures:
https://lab.llvm.org/buildbot/#/builders/173/builds/10304

Another step towards getting rid of dependencies to the legacy
pass manager.

Primary change here is to just do -passes=foo instead of -foo in
simple situations (when running a single transform pass). But also
updated a few test running multiple passes.

Also removed some "duplicated" RUN lines in a few tests that where
using both -foo and -passes=foo syntax. No need to do the same kind
of testing twice.

 This patch adds the assembly/disassembly for the following instruction:
  SQDMULH (multiple vectors): Multi-vector signed saturating doubling multiply high.
For 2 and 4 ZA registers

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/SME-Instructions/SQDMULH--multiple-vectors---Multi-vector-signed-saturating-doubling-multiply-high-?lang=en

Depends on: D135563

Differential Revision: https://reviews.llvm.org/D135575

This patch adds the assembly/disassembly for the following instructions:

FCLAMP : Floating-point clamp to minimum/maximum number

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D136358

For some reason the initial deferred concepts patch didn't add this
check, which someone noticed could cause a problem with other patches
applied.  This makes sure we check these, so that an error condition
cannot cause us to crash.

This makes the code forward-compatible to the memory attribute.

The crash comes from mismatch between load count in epilogue and seh instruction count.
Still because of the pass AArch64LoadStoreOpt. It remove some load in the epilogue but haven't remove the corresponding seh instruction.
This patch don't optimize the load in the epilogue to fix the issue.

Fix: #58516

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D136430

First patch in a series adding MC layer support for SVE2.1.

This patch adds the following feature:

sve2p1

Some of the existing SVE instructions added for SME are now
also available under the sve2p1 feature, which are now guarded
by the HasSVE2p1orSME predicate.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D136352

D129213 improves verification of LiveVariables, and caused
CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll to fail with:
*** Bad machine code: LiveVariables: Block should not be in AliveBlocks ***
after Two-Address instruction pass.

Fix it by clearing AliveBlocks for a register which is no longer used.

Differential Revision: https://reviews.llvm.org/D136445

This patch adds the assembly/disassembly for the following instructions:
INT :
  ADD (array accumulators): Add multi-vector to ZA array vector accumulators.
  SUB  (array accumulators): Subtract multi-vector from ZA array vector accumulators.
FP:
  FADD : Floating-point add multi-vector to ZA array vector accumulators.
  FSUB : Floating-point subtract multi-vector from ZA array vector accumulators.
For  Two and Four ZA single-vectors

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Depends on: D135563

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D135567

Differential Revision: https://reviews.llvm.org/D136431

This patch implements
Int:
  SQCVT: Multi-vector signed saturating extract narrow for 2 and 4 registers.
  UQCVT: Multi-vector unsigned saturating extract narrow for 2 and 4 registers.
  SQCVTU: Multi-vector signed saturating unsigned extract narrow for 2 and 4 registers
  SQCVTN:  Multi-vector signed saturating extract narrow and interleave.
  SQCVTUN: Multi-vector signed saturating unsigned extract narrow and interleave.
  UQCVTN: Multi-vector unsigned saturating extract narrow and interleave.

FP:
  FCVT(narrowing): Multi-vector floating-point convert from single-precision to
                  packed half-precision.
  FCVTN: Multi-vector floating-point convert from single-precision to
           interleaved half-precision.
  BFCVT: Multi-vector floating-point convert from single-precision to packed
         BFloat16 format.
  BFCVTN: : Multi-vector floating-point convert from single-precision to
            interleaved BFloat16 format.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Depends on: D135563

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D135588

This patch adds the assembly/disassembly for the following instructions:
  INT:
     SMLAL
     SMLSL
     UMLAL
     UMLSL
  FP:
    BFMLAL
    BFMLSL
    FMLAL
    FMLSL
For multiple and indexed vector, Multiple and Single vector and
Multi vectors, for 1, 2 and 4 ZA registers.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

It also adds a new immediate:
  uimm3s2range for off3
  uimm2s2range for off2
to represent the vector select offset.
The new operands have the range between the first and the last vector position.

Depends on: D135563

Reviewed By: aemerson, sdesmalen

Re-landing the patch as the problem with https://reviews.llvm.org/D135563
is fixed in this commit: 1e4f82c2

Differential Revision: https://reviews.llvm.org/D135785

This is useful for clients that want to highlight constructors and
destructors different from classes, e.g. like functions.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D134728

This allows the regular bitwise logic opcodes in addition to the
poison-safe select variants:
https://alive2.llvm.org/ce/z/8xB9gy

Handling commuted variants safely is likely trickier, so that's
left to another patch.