1. Jul 06, 2019
  2. Jul 05, 2019
    • Matt Arsenault's avatar
      ScheduleDAG: Fix incorrectly killing registers in bundles · 27a6985d
      Matt Arsenault authored
      When looking for uses/defs to add kill flags, the iterator was double
      incremented, skipping the first instruction in the bundle. The use
      register in the first bundle instruction was then incorrectly killed.
      The "First" instruction should be the BUNDLE itself as the proper
      reverse iterator endpoint.
      
      llvm-svn: 365216
      27a6985d
    • Eugene Leviant's avatar
      [ThinLTO] Attempt to recommit r365188 after alignment fix · 3aef3528
      Eugene Leviant authored
      llvm-svn: 365215
      3aef3528
    • David Green's avatar
      [ARM] MVE patterns for VMVN, VORR and VBIC · 47afdaa4
      David Green authored
      This add simple Q register forms of bitwise not instructions.
      
      Differential Revision: https://reviews.llvm.org/D63983
      
      llvm-svn: 365214
      47afdaa4
    • Nico Weber's avatar
      gn build: Merge r365203 · df173bf9
      Nico Weber authored
      llvm-svn: 365213
      df173bf9
    • Nico Weber's avatar
      Add a comment explaining why a function exists · 2bca3d4f
      Nico Weber authored
      llvm-svn: 365212
      2bca3d4f
    • Jay Foad's avatar
      [AMDGPU] DPP combiner: recognize identities for more opcodes · 7e0c10b5
      Jay Foad authored
      Summary:
      This allows the DPP combiner to kick in more often. For example the
      exclusive scan generated by the atomic optimizer for a divergent atomic
      add used to look like this:
      
              v_mov_b32_e32 v3, v1
              v_mov_b32_e32 v5, v1
              v_mov_b32_e32 v6, v1
              v_mov_b32_dpp v3, v2  wave_shr:1 row_mask:0xf bank_mask:0xf
              s_nop 1
              v_add_u32_dpp v4, v3, v3  row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
              v_mov_b32_dpp v5, v3  row_shr:2 row_mask:0xf bank_mask:0xf
              v_mov_b32_dpp v6, v3  row_shr:3 row_mask:0xf bank_mask:0xf
              v_add3_u32 v3, v4, v5, v6
              v_mov_b32_e32 v4, v1
              s_nop 1
              v_mov_b32_dpp v4, v3  row_shr:4 row_mask:0xf bank_mask:0xe
              v_add_u32_e32 v3, v3, v4
              v_mov_b32_e32 v4, v1
              s_nop 1
              v_mov_b32_dpp v4, v3  row_shr:8 row_mask:0xf bank_mask:0xc
              v_add_u32_e32 v3, v3, v4
              v_mov_b32_e32 v4, v1
              s_nop 1
              v_mov_b32_dpp v4, v3  row_bcast:15 row_mask:0xa bank_mask:0xf
              v_add_u32_e32 v3, v3, v4
              s_nop 1
              v_mov_b32_dpp v1, v3  row_bcast:31 row_mask:0xc bank_mask:0xf
              v_add_u32_e32 v1, v3, v1
              v_add_u32_e32 v1, v2, v1
              v_readlane_b32 s0, v1, 63
      
      But now most of the dpp movs are combined into adds:
      
              v_mov_b32_e32 v3, v1
              v_mov_b32_e32 v5, v1
              s_nop 0
              v_mov_b32_dpp v3, v2  wave_shr:1 row_mask:0xf bank_mask:0xf
              s_nop 1
              v_add_u32_dpp v4, v3, v3  row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
              v_mov_b32_dpp v5, v3  row_shr:2 row_mask:0xf bank_mask:0xf
              v_mov_b32_dpp v1, v3  row_shr:3 row_mask:0xf bank_mask:0xf
              v_add3_u32 v1, v4, v5, v1
              s_nop 1
              v_add_u32_dpp v1, v1, v1  row_shr:4 row_mask:0xf bank_mask:0xe
              s_nop 1
              v_add_u32_dpp v1, v1, v1  row_shr:8 row_mask:0xf bank_mask:0xc
              s_nop 1
              v_add_u32_dpp v1, v1, v1  row_bcast:15 row_mask:0xa bank_mask:0xf
              s_nop 1
              v_add_u32_dpp v1, v1, v1  row_bcast:31 row_mask:0xc bank_mask:0xf
              v_add_u32_e32 v1, v2, v1
              v_readlane_b32 s0, v1, 63
      
      Reviewers: arsenm, vpykhtin
      
      Subscribers: kzhuravl, nemanjai, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kbarton, MaskRay, jfb, llvm-commits
      
      Tags: #llvm
      
      Differential Revision: https://reviews.llvm.org/D64207
      
      llvm-svn: 365211
      7e0c10b5
    • Hamza Sood's avatar
      NFC: Add an explicit return for safety and consistency · d14003d9
      Hamza Sood authored
      This case implicitly falls-through, which is fine now as it's at the end of the
      function, but it seems like an accident waiting to happen.
      
      llvm-svn: 365210
      d14003d9