The `scf.index_switch` is a control-flow operation that branches to one of the
given regions based on the values of the argument and the cases. The
argument is always of type `index`.

Example:

```mlir
%0 = scf.index_switch %arg0 -> i32
case 2 {
  %1 = arith.constant 10 : i32
  scf.yield %1 : i32
}
case 5 {
  %2 = arith.constant 20 : i32
  scf.yield %2 : i32
}
default {
  %3 = arith.constant 30 : i32
  scf.yield %3 : i32
}
```

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D136003

I often run llvm-reduce on IR that contains debug info, this prevents an
extra step of `opt -passes=strip` I do every time and will result in a
lot less invalid reductions around debug metadata.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D136208

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136411

This does not appear to affect codegen, but using SGPR classes for
operands of VALU instructions looked weird.

Differential Revision: https://reviews.llvm.org/D136459

Outline the code that generates the loop structure to iterate over a dense
tensor or a sparse constant to genDenseTensorOrSparseConstantIterLoop.

Move a few routines to CodegenUtils for sharing.

Reviewed By: wrengr

Differential Revision: https://reviews.llvm.org/D136210

Verify the LiveVariables analysis after a pass that claims to preserve
it, even if there are no further passes (apart from the verifier itself)
that would use the analysis.

Differential Revision: https://reviews.llvm.org/D129213

This is obviously correct for real logic instructions,
and it also works for the poison-safe variants that use
selects:
https://alive2.llvm.org/ce/z/wyHiwX

This is motivated by the lack of 'xor' folding seen in issue #58313.
This more general fold should help reduce some of those patterns,
but I'm not sure if this specific case does anything for that
particular example.

Separating the matches makes it easier
to enhance for commutative patterns.

FIRSupports includes headers from HLFIRDialect that are generated at
compile time. Therefore it must wait until these headers have been
generated.

Fix flang bot failures:
https://lab.llvm.org/buildbot/#/builders/173/builds/10304

Another step towards getting rid of dependencies to the legacy
pass manager.

Primary change here is to just do -passes=foo instead of -foo in
simple situations (when running a single transform pass). But also
updated a few test running multiple passes.

Also removed some "duplicated" RUN lines in a few tests that where
using both -foo and -passes=foo syntax. No need to do the same kind
of testing twice.

 This patch adds the assembly/disassembly for the following instruction:
  SQDMULH (multiple vectors): Multi-vector signed saturating doubling multiply high.
For 2 and 4 ZA registers

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/SME-Instructions/SQDMULH--multiple-vectors---Multi-vector-signed-saturating-doubling-multiply-high-?lang=en

Depends on: D135563

Differential Revision: https://reviews.llvm.org/D135575

This patch adds the assembly/disassembly for the following instructions:

FCLAMP : Floating-point clamp to minimum/maximum number

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D136358

For some reason the initial deferred concepts patch didn't add this
check, which someone noticed could cause a problem with other patches
applied.  This makes sure we check these, so that an error condition
cannot cause us to crash.

This makes the code forward-compatible to the memory attribute.

The crash comes from mismatch between load count in epilogue and seh instruction count.
Still because of the pass AArch64LoadStoreOpt. It remove some load in the epilogue but haven't remove the corresponding seh instruction.
This patch don't optimize the load in the epilogue to fix the issue.

Fix: #58516

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D136430

First patch in a series adding MC layer support for SVE2.1.

This patch adds the following feature:

sve2p1

Some of the existing SVE instructions added for SME are now
also available under the sve2p1 feature, which are now guarded
by the HasSVE2p1orSME predicate.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D136352

D129213 improves verification of LiveVariables, and caused
CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll to fail with:
*** Bad machine code: LiveVariables: Block should not be in AliveBlocks ***
after Two-Address instruction pass.

Fix it by clearing AliveBlocks for a register which is no longer used.

Differential Revision: https://reviews.llvm.org/D136445

This patch adds the assembly/disassembly for the following instructions:
INT :
  ADD (array accumulators): Add multi-vector to ZA array vector accumulators.
  SUB  (array accumulators): Subtract multi-vector from ZA array vector accumulators.
FP:
  FADD : Floating-point add multi-vector to ZA array vector accumulators.
  FSUB : Floating-point subtract multi-vector from ZA array vector accumulators.
For  Two and Four ZA single-vectors

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Depends on: D135563

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D135567

Differential Revision: https://reviews.llvm.org/D136431

This patch implements
Int:
  SQCVT: Multi-vector signed saturating extract narrow for 2 and 4 registers.
  UQCVT: Multi-vector unsigned saturating extract narrow for 2 and 4 registers.
  SQCVTU: Multi-vector signed saturating unsigned extract narrow for 2 and 4 registers
  SQCVTN:  Multi-vector signed saturating extract narrow and interleave.
  SQCVTUN: Multi-vector signed saturating unsigned extract narrow and interleave.
  UQCVTN: Multi-vector unsigned saturating extract narrow and interleave.

FP:
  FCVT(narrowing): Multi-vector floating-point convert from single-precision to
                  packed half-precision.
  FCVTN: Multi-vector floating-point convert from single-precision to
           interleaved half-precision.
  BFCVT: Multi-vector floating-point convert from single-precision to packed
         BFloat16 format.
  BFCVTN: : Multi-vector floating-point convert from single-precision to
            interleaved BFloat16 format.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Depends on: D135563

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D135588

This patch adds the assembly/disassembly for the following instructions:
  INT:
     SMLAL
     SMLSL
     UMLAL
     UMLSL
  FP:
    BFMLAL
    BFMLSL
    FMLAL
    FMLSL
For multiple and indexed vector, Multiple and Single vector and
Multi vectors, for 1, 2 and 4 ZA registers.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

It also adds a new immediate:
  uimm3s2range for off3
  uimm2s2range for off2
to represent the vector select offset.
The new operands have the range between the first and the last vector position.

Depends on: D135563

Reviewed By: aemerson, sdesmalen

Re-landing the patch as the problem with https://reviews.llvm.org/D135563
is fixed in this commit: 1e4f82c2

Differential Revision: https://reviews.llvm.org/D135785

This is useful for clients that want to highlight constructors and
destructors different from classes, e.g. like functions.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D134728

This allows the regular bitwise logic opcodes in addition to the
poison-safe select variants:
https://alive2.llvm.org/ce/z/8xB9gy

Handling commuted variants safely is likely trickier, so that's
left to another patch.

This patch adds the assembly/disassembly for the following instructions:
  ADD (to vector): Add replicated single vector to multi-vector with multi-vector result.
  SQDMULH (multiple and single vector): Multi-vector signed saturating doubling multiply high by vector.
for 2 and 4 ZA SVE registers.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

It also adds more size for the multiple register tuple:
  ZZ_b_mul_r,  ZZ_h_mul_r,
  ZZZZ_b_mul_r,  ZZZZ_h_mul_r,
for 8 bits and 16 bits with 2 and 4 ZA registers.

Depends on: D135468

With a fix for Mips for this test:
llvm/test/MC/Mips/mips64r6/valid.s

Differential Revision: https://reviews.llvm.org/D135563

This patch teaches the `CPlusPlusNameParser` to parse the
demangled/prettified [[gnu::abi_tag(...)]] attribute. The demangled format
isn't standardized and the additions to the parser were mainly driven
using Clang (and the limited information on this from the official
Clang docs).

This change is motivated by multiple failures around step-in
behaviour for libcxx APIs (many of which have ABI tags as of recently).
LLDB determines whether the `step-avoid-regexp` matches the current
frame by parsing the scope-qualified name out of the demangled
function symbol. On failure, the `CPlusPlusNameParser` will simply
return the fully demangled name (which can include the return type)
to the caller, which in `FrameMatchesAvoidCriteria` means we will
not correctly decide whether we should stop at a frame or not if
the function has an abi_tag.

Ideally we wouldn't want to rely on the non-standard format
of demangled attributes. Alternatives would be:

1....

fir.dispatch code generation was not handling fir.class pointer and
allocatable types. Update the code generation part to rertieve correctly the
the type info from those types.

Depends on D136426

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D136429

When allocating a polymorphic entity, its type descriptor can come
from the declared type or can be provided in the allocate statement.
This patch adds lowering for allocate on polymorphic by calling
the `AllocatableInitDerived` runtime function with the correct
type descriptor. Some adaptation are made in the code generation
to accept fir.class where it is appropriate.

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D136426

Update links to googletest documentation
No automatic tests, but local manual test: i click it, it opens the googletest documentation.

Reviewed By: sylvestre.ledru

Differential Revision: https://reviews.llvm.org/D136424

https://reviews.llvm.org/D136428 introduced the need for FIRBuilder
library to link against HLFIRDialect to satisfy shared builds.

The PrintFlangFunctionNames failure is unrelated, it is a build
race because many of the headers included in FrontendAction are
tablegen generated. So PrintFlangFunctionNames must wait until its
headers can be safely used. See
https://lab.llvm.org/buildbot/#/builders/191/builds/10340

The `__has_constexpr_builtin` macro can be used to check
whether the builtin in constant-evaluated by Clang frontend.

Reviewed By: aaron.ballman, shafik

Differential Revision: https://reviews.llvm.org/D136036

Add hlfir::FortranEntity class and a first helper to convert it to
fir::ExtendedValue.

The hlfir::FortranEntity will be the core class of the new expression
lowering. It is conceptually very similar to what fir::ExtendedValue
is today, except that it is wrapping single mlir::Value: it holds the
SSA value for a lowered Fortran variable or expression value.

Differential Revision: https://reviews.llvm.org/D136428

This code, on all platforms was a use-after-move violation that resulted
in the if-statement always returning false. As several core tests specifically
tested that this code did not execute, we assume that is the intent and
match behavior to existing behavior without relying on use-after-move
results.

This patch adds the basic dialect definition of the HLFIR dialect that
was described in https://reviews.llvm.org/D134285.

It adds the definition of the hlfir.expr type and related tests so that
it can be verified that the dialect is properly hooked up by the tools.

Operations will be added as progress is made in the expression
lowering update.

Differential Revision: https://reviews.llvm.org/D136328

Replace the two-level implementation with a simpler one that directly subclasses
the predicates, avoiding the instantiation of the template to get the `type`
member in a situation where we should short-circuit. This prevents incorrect
diagnostics when the instantiated predicate contains a static assertion.

Add a test case that reproduced the previous problem. The existing test case
involving `HasNoValue` didn't catch the problem because `HasNoValue` was in the
final position. The bug comes up when the predicate that shouldn't be
instantiated is after the short-circuit position but there is more to follow,
because then `__conjunction_impl<False, BadPredicate, ...>` instantiates
`__conjunction_impl<BadPredicate, ...>` (in order to obtain its `type` member),
which in turn instantiates `BadPredicate` in order to obtain its `value` member.

In contrast the new implementation doesn't recurse in instantiation any further
than it needs to, because i...

Enable Machine Combiner for O1/O2/O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.

Originally it was enabled only for -O3, however I looked through time reports
and usually it takes 0.1%-0.4% of total time, and never takes more than 1.0%.

Differential Revision: https://reviews.llvm.org/D136339

This makes sure that this code continue working when switching to
the memory attribute.

A caveat here is that onlyReadsMemory() will also true for readnone.
To be conservative, I'm explicitly excluding that case here.