Cleanup the interface in preparation for hierarchical page tables.

v2: add incr parameter to set_page for simple scattered PTs uptates
    added PDE-specific flags to r600_flags and radeon_drm.h
    removed superfluous value masking with 0xffffffff

v3: removed superfluous bo_va->valid checking
    changed R600_PTE_VALID to R600_ENTRY_VALID to handle PDE too

v4 (ck): fix indention style, rework and fix typos in commit message,
         add documentation for incr parameter, also use incr
         parameter for system pages

v5 (agd5f): use upper_32_bits() and minor white space fixes

Signed-off-by: Christian König <deathsimple@vodafone.de>
Signed-off-by: Dmitry Cherkassov <Dmitrii.Cherkasov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Restructure the code to jump out via labels instead of directly returning
early. Also make error reporting consistent across all hardware generations.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Simon Kitching <skitching@vonos.net>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Restore the backlight level on resume.  Some systems
need to explicitly restore the backlight level on
resume.

Fixes panel resume on my Trinity laptop and may fix the
following bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=43829
https://bugzilla.kernel.org/show_bug.cgi?id=46241



Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Read back the backlight level from the hw.
Needed for proper backlight restoration on resume.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

SI asics store voltage information differently so we
don't have a way to deal with it properly yet.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

This allows us to bail if we can't support the requested
setup from a PPLL perspective.  Prevents broken setups
from being attempted.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Since the current KMS API sets the mode independantly on
each crtc, we may end up with resource conflicts.  The PLL
allocation is one of those cases.  In the following example
we have 3 crtcs in use driving 2 DVI connectors and 1 DP
connector.  On the initial kernel modeset for fbdev, the
display topology ends up as follows:

crtc0 -> DP-0
crtc1 -> DVI-0
crtc2 -> DVI-1

Because this is the first modeset, all of the PLLs are
available as none have been assigned.  So we end up with
the following:

crtc0 uses DCPLL
crtc1 uses PPLL2
crtc2 uses PPLL1

When X starts, it assigns a different topology:

crtc0 -> DVI-0
crtc1 -> DP-0
crtc2 -> DVI-1

However, since the KMS API is per crtc, we set the mode on each
crtc independantly.  When it comes time to set the mode on crtc0,
the topology for crtc1 and crtc2 are still intact.  crtc1 and
crtc2 are already assigned PPLL2 and PPLL1 so when it comes time
to set the mode on crtc0, crtc1 and crtc2 have not been torn down
yet, so there appears to be no PLLs available.  In reality, we
are reconfiguring the entire display topology, however, since
each crtc is handled independantly, we don't know that in the
driver at each crtc mode set time.

This patch checks to see if the same connector is being driven by
another crtc, and if so, uses the PLL already associated with it.

v2: store connector in the radeon crtc struct, simplify checking.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Compare the adjusted clock as well as the crtc mode
clock.  This handles cases where the driver adjusts
the clock for specific special cases.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This saves lots of lookups later.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

We need the calculate the pixel clock before allocating a PPLL
in order to insure the clocks really match.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

If several non-DP displays use the same pixel clock
we can use the same PPLL for all of them.  If all
relevant displays have the same pixel clock, this
allows the driver to:
- use fewer PPLLs which saves power
- support more than two non-DP displays on DCE4+

The current drm modesetting infrastructure doesn't
really provide a good framework for validating combinations
that work or won't work, so it's possible you could go from
a working configuration to a non-working one by changing the
mode a one of the displays.  However, there this is better
than what was there before.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

If possible, use a single PPLL for multiple DP displays
on DCE3.x.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

For DP we can use the same PPLL for all active DP
encoders.  Take advantage of that to prevent cases
where we may end up sharing a PPLL between DP and
non-DP which won't work.  Also clean up the code
a bit.

v2: - fix missing pll_id assignment in crtc init
v3: - fix DP PPLL check
    - document functions
    - break in main encoder search loop after matching.
      no need to keep checking additional encoders.
v4: - same as v3, but re-apply to drm-next as the corner
      cases are fixed properly in subsequent patches.

fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=54471



Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

comparing the encoder mode to the encoder id for DVO.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

MiscInfo field should be programmed with the crtc id
rather than the pll id.  However, at this point the
two are the same for chips with this version of the table.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Makes it more consistent with the surrounding code.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Use the proper struct in the union.  That field
has the same offset in every struct, so no functional
change.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Roughly based on how nouveau is handling it. Instead of
adding the bo_va when the address is set add the bo_va
when the handle is opened, but set the address to zero
until userspace tells us where to place it.

This fixes another bunch of problems with glamor.

v2: agd5f: fix build after dropping patch 7/8.

Signed-off-by: Christian König <deathsimple@vodafone.de>

Make the reserve non interruptible.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

The no_wait param isn't used anywhere, and actually isn't
very usefull at all.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

It doesn't really belong into the object functions,
also rename it to avoid collisions with struct radeon_bo_va.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

Even GPUs can have a null pointer dereference, so move
the IB pool to another offset to catch those.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

The end offset is exclusive not inclusive.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

When a VM is used on more than one ring we need to
sync to the last user.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

This applies on top of drm/radeon: Mark all possible functions / structs as static.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Let's allow GCC to optimize better.

This exposed some five unused functions, but this patch doesn't remove them.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Was removed in the async VM update series.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Don't read past the end of the array if we encounter an unknown
thermal controller.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Currently doing the update with the CP.

v2: Rebased on Jeromes bugfix. Make validity comparison
    more human readable.

Signed-off-by: Christian König <deathsimple@vodafone.de>

Make sure that the ib bo is bound and is page table is up to date
in the virtual address space.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

Makes it easier to move it into the rings.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

Removing the need to wait for anything.

Still not ideal, since we need to free pt on va remove.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

Move binding onto the ring, simplifying handling a bit.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

Move flushing the VMs as function into the rings.
First step to make VM operations async.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

It actually isn't very useful.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

So it looks more like the rest of the driver.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

Store a reference to the VM into the IB structure, that
makes calculating the IBs address a bit less complicated.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>