Loading drivers/gpu/drm/radeon/radeon.h +19 −16 Original line number Diff line number Diff line Loading @@ -641,28 +641,12 @@ struct radeon_vm { struct radeon_fence *fence; }; struct radeon_vm_funcs { int (*init)(struct radeon_device *rdev); void (*fini)(struct radeon_device *rdev); /* cs mutex must be lock for schedule_ib */ int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id); void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm); void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm); uint32_t (*page_flags)(struct radeon_device *rdev, struct radeon_vm *vm, uint32_t flags); void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm, unsigned pfn, uint64_t addr, uint32_t flags); }; struct radeon_vm_manager { struct mutex lock; struct list_head lru_vm; uint32_t use_bitmap; struct radeon_sa_manager sa_manager; uint32_t max_pfn; /* fields constant after init */ const struct radeon_vm_funcs *funcs; /* number of VMIDs */ unsigned nvm; /* vram base address for page table entry */ Loading Loading @@ -1128,6 +1112,18 @@ struct radeon_asic { void (*tlb_flush)(struct radeon_device *rdev); int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); } gart; struct { int (*init)(struct radeon_device *rdev); void (*fini)(struct radeon_device *rdev); int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id); void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm); void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm); uint32_t (*page_flags)(struct radeon_device *rdev, struct radeon_vm *vm, uint32_t flags); void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm, unsigned pfn, uint64_t addr, uint32_t flags); } vm; /* ring specific callbacks */ struct { void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); Loading Loading @@ -1735,6 +1731,13 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) #define radeon_asic_vm_bind(rdev, v, id) (rdev)->asic->vm.bind((rdev), (v), (id)) #define radeon_asic_vm_unbind(rdev, v) (rdev)->asic->vm.unbind((rdev), (v)) #define radeon_asic_vm_tlb_flush(rdev, v) (rdev)->asic->vm.tlb_flush((rdev), (v)) #define radeon_asic_vm_page_flags(rdev, v, flags) (rdev)->asic->vm.page_flags((rdev), (v), (flags)) #define radeon_asic_vm_set_page(rdev, v, pfn, addr, flags) (rdev)->asic->vm.set_page((rdev), (v), (pfn), (addr), (flags)) #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) Loading drivers/gpu/drm/radeon/radeon_asic.c +27 −23 Original line number Diff line number Diff line Loading @@ -1358,16 +1358,6 @@ static struct radeon_asic btc_asic = { }, }; static const struct radeon_vm_funcs cayman_vm_funcs = { .init = &cayman_vm_init, .fini = &cayman_vm_fini, .bind = &cayman_vm_bind, .unbind = &cayman_vm_unbind, .tlb_flush = &cayman_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }; static struct radeon_asic cayman_asic = { .init = &cayman_init, .fini = &cayman_fini, Loading @@ -1382,6 +1372,15 @@ static struct radeon_asic cayman_asic = { .tlb_flush = &cayman_pcie_gart_tlb_flush, .set_page = &rs600_gart_set_page, }, .vm = { .init = &cayman_vm_init, .fini = &cayman_vm_fini, .bind = &cayman_vm_bind, .unbind = &cayman_vm_unbind, .tlb_flush = &cayman_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }, .ring = { [RADEON_RING_TYPE_GFX_INDEX] = { .ib_execute = &cayman_ring_ib_execute, Loading Loading @@ -1477,6 +1476,15 @@ static struct radeon_asic trinity_asic = { .tlb_flush = &cayman_pcie_gart_tlb_flush, .set_page = &rs600_gart_set_page, }, .vm = { .init = &cayman_vm_init, .fini = &cayman_vm_fini, .bind = &cayman_vm_bind, .unbind = &cayman_vm_unbind, .tlb_flush = &cayman_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }, .ring = { [RADEON_RING_TYPE_GFX_INDEX] = { .ib_execute = &cayman_ring_ib_execute, Loading Loading @@ -1558,16 +1566,6 @@ static struct radeon_asic trinity_asic = { }, }; static const struct radeon_vm_funcs si_vm_funcs = { .init = &si_vm_init, .fini = &si_vm_fini, .bind = &si_vm_bind, .unbind = &si_vm_unbind, .tlb_flush = &si_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }; static struct radeon_asic si_asic = { .init = &si_init, .fini = &si_fini, Loading @@ -1582,6 +1580,15 @@ static struct radeon_asic si_asic = { .tlb_flush = &si_pcie_gart_tlb_flush, .set_page = &rs600_gart_set_page, }, .vm = { .init = &si_vm_init, .fini = &si_vm_fini, .bind = &si_vm_bind, .unbind = &si_vm_unbind, .tlb_flush = &si_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }, .ring = { [RADEON_RING_TYPE_GFX_INDEX] = { .ib_execute = &si_ring_ib_execute, Loading Loading @@ -1789,13 +1796,11 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->asic = &cayman_asic; /* set num crtcs */ rdev->num_crtc = 6; rdev->vm_manager.funcs = &cayman_vm_funcs; break; case CHIP_ARUBA: rdev->asic = &trinity_asic; /* set num crtcs */ rdev->num_crtc = 4; rdev->vm_manager.funcs = &cayman_vm_funcs; break; case CHIP_TAHITI: case CHIP_PITCAIRN: Loading @@ -1803,7 +1808,6 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->asic = &si_asic; /* set num crtcs */ rdev->num_crtc = 6; rdev->vm_manager.funcs = &si_vm_funcs; break; default: /* FIXME: not supported yet */ Loading drivers/gpu/drm/radeon/radeon_gart.c +8 −8 Original line number Diff line number Diff line Loading @@ -448,7 +448,7 @@ int radeon_vm_manager_init(struct radeon_device *rdev) return r; } r = rdev->vm_manager.funcs->init(rdev); r = radeon_asic_vm_init(rdev); if (r) return r; Loading Loading @@ -476,7 +476,7 @@ int radeon_vm_manager_init(struct radeon_device *rdev) } } r = rdev->vm_manager.funcs->bind(rdev, vm, vm->id); r = radeon_asic_vm_bind(rdev, vm, vm->id); if (r) { DRM_ERROR("Failed to bind vm %d!\n", vm->id); } Loading Loading @@ -522,7 +522,7 @@ static void radeon_vm_unbind_locked(struct radeon_device *rdev, radeon_fence_unref(&vm->fence); /* hw unbind */ rdev->vm_manager.funcs->unbind(rdev, vm); radeon_asic_vm_unbind(rdev, vm); rdev->vm_manager.use_bitmap &= ~(1 << vm->id); list_del_init(&vm->list); vm->id = -1; Loading Loading @@ -553,7 +553,7 @@ void radeon_vm_manager_fini(struct radeon_device *rdev) list_for_each_entry_safe(vm, tmp, &rdev->vm_manager.lru_vm, list) { radeon_vm_unbind_locked(rdev, vm); } rdev->vm_manager.funcs->fini(rdev); radeon_asic_vm_fini(rdev); mutex_unlock(&rdev->vm_manager.lock); radeon_sa_bo_manager_suspend(rdev, &rdev->vm_manager.sa_manager); Loading Loading @@ -639,7 +639,7 @@ int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm) } /* do hw bind */ r = rdev->vm_manager.funcs->bind(rdev, vm, id); r = radeon_asic_vm_bind(rdev, vm, id); if (r) { radeon_sa_bo_free(rdev, &vm->sa_bo, NULL); return r; Loading Loading @@ -830,14 +830,14 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev, } } pfn = bo_va->soffset / RADEON_GPU_PAGE_SIZE; flags = rdev->vm_manager.funcs->page_flags(rdev, bo_va->vm, bo_va->flags); flags = radeon_asic_vm_page_flags(rdev, bo_va->vm, bo_va->flags); for (i = 0, addr = 0; i < ngpu_pages; i++) { if (mem && bo_va->valid) { addr = radeon_vm_get_addr(rdev, mem, i); } rdev->vm_manager.funcs->set_page(rdev, bo_va->vm, i + pfn, addr, flags); radeon_asic_vm_set_page(rdev, bo_va->vm, i + pfn, addr, flags); } rdev->vm_manager.funcs->tlb_flush(rdev, bo_va->vm); radeon_asic_vm_tlb_flush(rdev, bo_va->vm); return 0; } Loading Loading
drivers/gpu/drm/radeon/radeon.h +19 −16 Original line number Diff line number Diff line Loading @@ -641,28 +641,12 @@ struct radeon_vm { struct radeon_fence *fence; }; struct radeon_vm_funcs { int (*init)(struct radeon_device *rdev); void (*fini)(struct radeon_device *rdev); /* cs mutex must be lock for schedule_ib */ int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id); void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm); void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm); uint32_t (*page_flags)(struct radeon_device *rdev, struct radeon_vm *vm, uint32_t flags); void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm, unsigned pfn, uint64_t addr, uint32_t flags); }; struct radeon_vm_manager { struct mutex lock; struct list_head lru_vm; uint32_t use_bitmap; struct radeon_sa_manager sa_manager; uint32_t max_pfn; /* fields constant after init */ const struct radeon_vm_funcs *funcs; /* number of VMIDs */ unsigned nvm; /* vram base address for page table entry */ Loading Loading @@ -1128,6 +1112,18 @@ struct radeon_asic { void (*tlb_flush)(struct radeon_device *rdev); int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); } gart; struct { int (*init)(struct radeon_device *rdev); void (*fini)(struct radeon_device *rdev); int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id); void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm); void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm); uint32_t (*page_flags)(struct radeon_device *rdev, struct radeon_vm *vm, uint32_t flags); void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm, unsigned pfn, uint64_t addr, uint32_t flags); } vm; /* ring specific callbacks */ struct { void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); Loading Loading @@ -1735,6 +1731,13 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) #define radeon_asic_vm_bind(rdev, v, id) (rdev)->asic->vm.bind((rdev), (v), (id)) #define radeon_asic_vm_unbind(rdev, v) (rdev)->asic->vm.unbind((rdev), (v)) #define radeon_asic_vm_tlb_flush(rdev, v) (rdev)->asic->vm.tlb_flush((rdev), (v)) #define radeon_asic_vm_page_flags(rdev, v, flags) (rdev)->asic->vm.page_flags((rdev), (v), (flags)) #define radeon_asic_vm_set_page(rdev, v, pfn, addr, flags) (rdev)->asic->vm.set_page((rdev), (v), (pfn), (addr), (flags)) #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) Loading
drivers/gpu/drm/radeon/radeon_asic.c +27 −23 Original line number Diff line number Diff line Loading @@ -1358,16 +1358,6 @@ static struct radeon_asic btc_asic = { }, }; static const struct radeon_vm_funcs cayman_vm_funcs = { .init = &cayman_vm_init, .fini = &cayman_vm_fini, .bind = &cayman_vm_bind, .unbind = &cayman_vm_unbind, .tlb_flush = &cayman_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }; static struct radeon_asic cayman_asic = { .init = &cayman_init, .fini = &cayman_fini, Loading @@ -1382,6 +1372,15 @@ static struct radeon_asic cayman_asic = { .tlb_flush = &cayman_pcie_gart_tlb_flush, .set_page = &rs600_gart_set_page, }, .vm = { .init = &cayman_vm_init, .fini = &cayman_vm_fini, .bind = &cayman_vm_bind, .unbind = &cayman_vm_unbind, .tlb_flush = &cayman_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }, .ring = { [RADEON_RING_TYPE_GFX_INDEX] = { .ib_execute = &cayman_ring_ib_execute, Loading Loading @@ -1477,6 +1476,15 @@ static struct radeon_asic trinity_asic = { .tlb_flush = &cayman_pcie_gart_tlb_flush, .set_page = &rs600_gart_set_page, }, .vm = { .init = &cayman_vm_init, .fini = &cayman_vm_fini, .bind = &cayman_vm_bind, .unbind = &cayman_vm_unbind, .tlb_flush = &cayman_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }, .ring = { [RADEON_RING_TYPE_GFX_INDEX] = { .ib_execute = &cayman_ring_ib_execute, Loading Loading @@ -1558,16 +1566,6 @@ static struct radeon_asic trinity_asic = { }, }; static const struct radeon_vm_funcs si_vm_funcs = { .init = &si_vm_init, .fini = &si_vm_fini, .bind = &si_vm_bind, .unbind = &si_vm_unbind, .tlb_flush = &si_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }; static struct radeon_asic si_asic = { .init = &si_init, .fini = &si_fini, Loading @@ -1582,6 +1580,15 @@ static struct radeon_asic si_asic = { .tlb_flush = &si_pcie_gart_tlb_flush, .set_page = &rs600_gart_set_page, }, .vm = { .init = &si_vm_init, .fini = &si_vm_fini, .bind = &si_vm_bind, .unbind = &si_vm_unbind, .tlb_flush = &si_vm_tlb_flush, .page_flags = &cayman_vm_page_flags, .set_page = &cayman_vm_set_page, }, .ring = { [RADEON_RING_TYPE_GFX_INDEX] = { .ib_execute = &si_ring_ib_execute, Loading Loading @@ -1789,13 +1796,11 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->asic = &cayman_asic; /* set num crtcs */ rdev->num_crtc = 6; rdev->vm_manager.funcs = &cayman_vm_funcs; break; case CHIP_ARUBA: rdev->asic = &trinity_asic; /* set num crtcs */ rdev->num_crtc = 4; rdev->vm_manager.funcs = &cayman_vm_funcs; break; case CHIP_TAHITI: case CHIP_PITCAIRN: Loading @@ -1803,7 +1808,6 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->asic = &si_asic; /* set num crtcs */ rdev->num_crtc = 6; rdev->vm_manager.funcs = &si_vm_funcs; break; default: /* FIXME: not supported yet */ Loading
drivers/gpu/drm/radeon/radeon_gart.c +8 −8 Original line number Diff line number Diff line Loading @@ -448,7 +448,7 @@ int radeon_vm_manager_init(struct radeon_device *rdev) return r; } r = rdev->vm_manager.funcs->init(rdev); r = radeon_asic_vm_init(rdev); if (r) return r; Loading Loading @@ -476,7 +476,7 @@ int radeon_vm_manager_init(struct radeon_device *rdev) } } r = rdev->vm_manager.funcs->bind(rdev, vm, vm->id); r = radeon_asic_vm_bind(rdev, vm, vm->id); if (r) { DRM_ERROR("Failed to bind vm %d!\n", vm->id); } Loading Loading @@ -522,7 +522,7 @@ static void radeon_vm_unbind_locked(struct radeon_device *rdev, radeon_fence_unref(&vm->fence); /* hw unbind */ rdev->vm_manager.funcs->unbind(rdev, vm); radeon_asic_vm_unbind(rdev, vm); rdev->vm_manager.use_bitmap &= ~(1 << vm->id); list_del_init(&vm->list); vm->id = -1; Loading Loading @@ -553,7 +553,7 @@ void radeon_vm_manager_fini(struct radeon_device *rdev) list_for_each_entry_safe(vm, tmp, &rdev->vm_manager.lru_vm, list) { radeon_vm_unbind_locked(rdev, vm); } rdev->vm_manager.funcs->fini(rdev); radeon_asic_vm_fini(rdev); mutex_unlock(&rdev->vm_manager.lock); radeon_sa_bo_manager_suspend(rdev, &rdev->vm_manager.sa_manager); Loading Loading @@ -639,7 +639,7 @@ int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm) } /* do hw bind */ r = rdev->vm_manager.funcs->bind(rdev, vm, id); r = radeon_asic_vm_bind(rdev, vm, id); if (r) { radeon_sa_bo_free(rdev, &vm->sa_bo, NULL); return r; Loading Loading @@ -830,14 +830,14 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev, } } pfn = bo_va->soffset / RADEON_GPU_PAGE_SIZE; flags = rdev->vm_manager.funcs->page_flags(rdev, bo_va->vm, bo_va->flags); flags = radeon_asic_vm_page_flags(rdev, bo_va->vm, bo_va->flags); for (i = 0, addr = 0; i < ngpu_pages; i++) { if (mem && bo_va->valid) { addr = radeon_vm_get_addr(rdev, mem, i); } rdev->vm_manager.funcs->set_page(rdev, bo_va->vm, i + pfn, addr, flags); radeon_asic_vm_set_page(rdev, bo_va->vm, i + pfn, addr, flags); } rdev->vm_manager.funcs->tlb_flush(rdev, bo_va->vm); radeon_asic_vm_tlb_flush(rdev, bo_va->vm); return 0; } Loading