- Mar 03, 2024
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Gabor Juhos authored
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: 2b46cd23 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support") Signed-off-by:
Gabor Juhos <j4g8y7@gmail.com> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240229-freq-table-terminator-v1-6-074334f0905c@gmail.com Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
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Gabor Juhos authored
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: ff93872a ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by:
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Gabor Juhos authored
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: d75b82cf ("clk: qcom: Add Global Clock Controller driver for IPQ9574") Signed-off-by:
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Gabor Juhos authored
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: 9607f622 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks") Signed-off-by:
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Gabor Juhos authored
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Only compile tested. Fixes: d9db07f0 ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by:
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Gabor Juhos authored
The frequency table arrays are supposed to be terminated with an empty element. Add such entry to the end of the arrays where it is missing in order to avoid possible out-of-bound access when the table is traversed by functions like qcom_find_freq() or qcom_find_freq_floor(). Fixes: e3fdbef1 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by:
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- Feb 17, 2024
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Konrad Dybcio authored
SDM845 downstream uses non-default values for GDSC internal waits. Program them accordingly to avoid surprises. Fixes: 81351776 ("clk: qcom: Add display clock controller driver for SDM845") Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # OnePlus 6 Link: https://lore.kernel.org/r/20240103-topic-845gdsc-v1-1-368efbe1a61d@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
This clock controller has never been used in the DT files merged to the kernel. According to Sibi, it only worked on the pre-production devices. For the production devices this functionality has been moved to the firmware. Drop the bindings now after dropping the driver itself. Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240216-drop-sc7180-mss-v1-2-0a8dc8d71c0c@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
This driver has never been used in the DT files merged to the kernel. According to Sibi, it only worked on the pre-production devices. For the production devices this functionality has been moved to the firmware. Drop the driver to remove possible confusion. Cc: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
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- Feb 15, 2024
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Konrad Dybcio authored
Instead of magically poking at the bit0 of branch clocks' CBCR, use the newly introduced helper. Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Konrad Dybcio authored
We hardcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Reviewed-by:
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- Feb 08, 2024
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Satya Priya Kakitapalli authored
The clk_init_data and pll_vco structures are never modified, make them const. Signed-off-by:
Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240201-dispcc-sm8150-v1-1-cbeb89015e5d@quicinc.com Signed-off-by:
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Manivannan Sadhasivam authored
Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 4433594b ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Acked-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-4-58a49d2f4605@linaro.org Signed-off-by:
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Bjorn Andersson authored
Merge the two SC8180X reset defines through a topic branch, to allow them being picked up in the DeviceTree source tree as well.
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Vladimir Lypak authored
Add new entries in the gcc driver for some more resets found on MSM8953. Signed-off-by:
Vladimir Lypak <vladimir.lypak@gmail.com> [luca: expand commit message, move entry, add more entries] Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Bjorn Andersson authored
Merge MSM8953 GCC DeviceTree binding update through topic branch, to allow it to be merged into DeviceTree source tree as well.
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Dmitry Baryshkov authored
There is no need to register video clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by:
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Dmitry Baryshkov authored
There is no need to register GPU clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by:
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Dmitry Baryshkov authored
There is no need to register display clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by:
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Dmitry Baryshkov authored
There is no need to register camera clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8350, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The Venus hw on 8650 is similar to the one on 8550, follow its requirements. Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8350, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 4450 being somewhat close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8280 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by:
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Konrad Dybcio authored
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8775 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by:
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Konrad Dybcio authored
Trying to toggle the resets in a rapid fashion can lead to the changes not actually arriving at the clock controller block when we expect them to. This was observed at least on SM8250. Read back the value after regmap_update_bits to ensure write completion. Fixes: b36ba30c ("clk: qcom: Add reset controller support") Signed-off-by:
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- Feb 07, 2024
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Manivannan Sadhasivam authored
Add missing QREF clocks for UFS MEM and UFS CARD controllers. Fixes: 0fadcdfd ("dt-bindings: clock: Add SC8180x GCC binding") Acked-by:
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Vladimir Lypak authored
Add new defines for some more BCRs found on MSM8953. Signed-off-by:
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Konrad Dybcio authored
They do the same thing, except the last argument of the last function call differs. Commonize them. Reviewed-by:
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Konrad Dybcio authored
u8 limits us to 255 microseconds of delay. Promote the delay variable to u16 to hold bigger values. Signed-off-by:
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