- Feb 11, 2010
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Michel Dänzer authored
It's happened time and time again (most recently with the support for EDID hardcoded in the BIOS ROM) that new code didn't check for rdev->bios being non-NULL before triggering dereferences of it. This would result in an oops/panic on setups with no BIOS ROM. Hopefully this central test will be more robust. Signed-off-by:
Michel Dänzer <daenzer@vmware.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Jerome Glisse authored
This patch add cs checker to r600/r700 hw. Command stream checking will rewrite some of the cs value in order to restrict GPU access to BO size. This doesn't break old userspace but just enforce safe value. It should break any things that was using the r600/r700 cs ioctl to do forbidden things (malicious software), though we are not aware of such things. Here is the list of thing we check : - enforcing resource size - enforcing color buffer slice tile max, will restrict cb access - enforcing db buffer slice tile max, will restrict db access We don't check for shader bigger than the BO in which they are supposed to be, such use would lead to GPU lockup and is harmless from security POV, as far as we can tell (note that even checking for this wouldn't prevent someone to write bogus shader that lead to lockup). This patch has received as much testing as humanly possible with old userspace to check that it didn't break such configuration. However not all the applications out there were tested, thus it might broke some odd, rare applications. [airlied: fix rules for cs checker for parallel builds] Signed-off-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
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Alex Deucher authored
original evergreen patches we against a kernel tree without my radeon i2c algo changes. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Alex Deucher authored
Fix a typo in crtc offset setup that set the crtc instances wrong for all crtcs except the first. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
Pre-pcie chips seem to use the reference clock rather than the sclk. Signed-off-by:
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- Feb 09, 2010
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Alex Deucher authored
This adds initial Evergreen KMS support, it doesn't include any acceleration features or interrupt handling yet. Major changes are DCE4 handling for PLLs for the > 2 crtcs. Signed-off-by:
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Alex Deucher authored
This merges ugly whitespace we want to keep for consistency along with the latest upstream changes. Signed-off-by:
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Jerome Glisse authored
This add an utilities function radeon_ib_bogus_add which will save an ib into a list of ib which can then be dumped using debugfs. Once dumped the ib is removed from the list. This should allow to save & capute ib for further debugging. Signed-off-by:
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Rafał Miłecki authored
This already simplifies code significally and makes it maintaible in case of adding memory reclocking plus voltage changing in future. Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
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Dave Airlie authored
For usec delays use udelay instead of scheduling, this should allow reclocking to happen faster. Signed-off-by: -
Alex Deucher authored
we need a constant sclk for i2c prescale. Also, get the current sclk when calculating prescale rather than using the default sclk. Signed-off-by:
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Alex Deucher authored
- only r4xx/r5xx/rs6xx/rs740 have clock gating atom table, so disable it on r6xx. it's already disabled on r7xx - check to make sure the clock_gating hook exists before calling it. This avoids a segfault on asics without that function. - remove unused static power management function. Signed-off-by:
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Rafał Miłecki authored
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Alex Deucher authored
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Alex Deucher authored
not hooked up yet. Signed-off-by:
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Alex Deucher authored
The idea is to flag a power state with a certain type and use that type to decide on what state to select. On r6xx+, we select a state and then transition between clock modes in that state. On pre-r6xx, we transition between states directly. Signed-off-by:
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Rafał Miłecki authored
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Alex Deucher authored
The general idea is to validate the current hw state against the set of power states and select a power state based on that. This patch just pulls the power states from the bios and prints the information. It is not currently hooked up in the actual power management code. Hooking it up will require reworking the the current power state selection code and will be handled in a future patch. Additionally, we'd need to decide on some default lower power states for cards without power tables. v2 - increment state_index after checking for default state v3 - fix typo in pm init on pre-atom cards, handle pre-atom cards without x86 bioses Signed-off-by:
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Alex Deucher authored
Currently unused. Signed-off-by:
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Rafał Miłecki authored
V2: reorganize functions, fix modesetting calls V3: rebase patch, use radeon's workqueue V4: enable on tested chipsets only, request VBLANK IRQs V5: enable PM on older hardware (IRQs, mode_fixup, dpms) V6: use separate dynpm module parameter V7: drop RADEON_ prefix, set minimum mode for dpms off V8: update legacy encoder call, fix order in rs600 IRQ V9: update compute_clocks call in legacy, not only DPMS_OFF Signed-off-by:
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Alex Deucher authored
Set the number of crtcs in rdev at crtc init and use it whenever we need the crtc count rather than recalculating it everytime. Signed-off-by:
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Alex Deucher authored
Only flush the gpu caches before we submit a fence. This leads to a small performance boost when we take the extra gpu cache flushes out of the ddx and mesa. Once this patch is in and the drm version is bumped, we can remove the flushes from the ddx and drm. Also, remove the extra cache flushes from the blit routine. Signed-off-by:
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Dave Airlie authored
Internal locking should be sufficent for all these cases. Signed-off-by: -
Alex Deucher authored
This is used in a lot of places in the atom encoder code. While here fix the spelling of crtc_source_params. Signed-off-by:
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Alex Deucher authored
use a union for the atom args. Signed-off-by:
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Alex Deucher authored
The panel on the Toshiba A300-1BU laptop does not like the PLL dividers selected by the avivo pll algo, but works fine using the older method. Add a quirk to handle it. Should fix fdo bug 26358. Signed-off-by: -
Alex Deucher authored
Rework the pll algo selection so that the pll algo in use can be selected more easily. This allows us to select different pll divider selection algos for specific monitors that work better with one algo or the other. This is needed for the next patch which adds an LVDS pll quirk for a specific notebook. Signed-off-by:
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Alex Deucher authored
Switch some magic numbers to their proper defines. The register header madness needs to be cleaned up at some point. Signed-off-by:
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Alex Deucher authored
Some servers hardcode an edid in rom so that they will work properly with KVMs. This is a port of the relevant code from the ddx. [airlied: reworked to validate edid at boot stage - and remove special quirk, if there is a valid EDID in the BIOS rom we'll just try and use it.] Signed-off-by:
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Alex Deucher authored
Some servers have two VGA ports but only report one in the bios connector tables. On these systems always set up the TV DAC so that it displays properly even if the bios is wrong. Signed-off-by:
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Alex Deucher authored
wire hw i2c support into radeon i2c algo. fixes merged: - handle bus probing correctly - use meaningful error numbers - abort if transaction fails - The line mapping is different depending on the asic. - protect hw i2c engine with a mutex - rs300 doesn't have a pin select bit - r200 has a different pin select setup Signed-off-by:
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- Feb 05, 2010
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Alex Deucher authored
Currently just a wrapper around bit algo Signed-off-by:
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Dave Airlie authored
This was incorrect according to the docs and the UMS driver does it like this. Signed-off-by: -
Dave Airlie authored
Boot testing on my rs480 laptop found the MC idle never happened on startup, a quick check with AMD found the idle bit is in a different place on the rs4xx than r300. Implement a new rs400 mc idle function to fix this. Signed-off-by: -
Dave Airlie authored
this was incorrect on my rs480. Signed-off-by: -
Dave Airlie authored
Support isn't correct yet and we are getting green tinges on the displays. Signed-off-by: -
Jerome Glisse authored
In suspend path we unmap the GART table while in cleaning up path we will unbind buffer and thus try to write to unmapped GART leading to oops. In order to avoid this we don't call the suspend path in cleanup path. Cleanup path is clever enough to desactive GPU like the suspend path is doing, thus this was redondant. Tested on: RV370, R420, RV515, RV570, RV610, RV770 (all PCIE) Signed-off-by:
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Andrew Morton authored
drivers/gpu/drm/radeon/radeon_combios.c: In function 'radeon_combios_get_lvds_info': drivers/gpu/drm/radeon/radeon_combios.c:893: warning: comparison is always false due to limited range of data type Cc: Dave Airlie <airlied@linux.ie> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Randy Dunlap authored
Fix ati_pcigart printk format warning: drivers/gpu/drm/ati_pcigart.c:115: warning: format '%Lx' expects type 'long long unsigned int', but argument 3 has type 'dma_addr_t' Signed-off-by:
Randy Dunlap <randy.dunlap@oracle.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Dave Airlie <airlied@linux.ie> Signed-off-by:
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