Commit f3ceebeb authored by Rex-BC Chen's avatar Rex-BC Chen Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: Add MediaTek CCI node for MT8183 



Add MediaTek CCI devfreq node for MT8183.

Signed-off-by: default avatarAndrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: default avatarRex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220516111130.13325-3-rex-bc.chen@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 95eacb24

arch/arm64/boot/dts/mediatek/mt8183-evb.dts

+4 −0
Original line number Diff line number Diff line
@@ -412,6 +412,10 @@ &spi5 { 


};



&cci {

	proc-supply = <&mt6358_vproc12_reg>;

};



&cpu0 {

	proc-supply = <&mt6358_vproc12_reg>;

};

arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -230,6 +230,10 @@ &auxadc { 
	status = "okay";

};



&cci {

	proc-supply = <&mt6358_vproc12_reg>;

};



&cpu0 {

	proc-supply = <&mt6358_vproc12_reg>;

};

arch/arm64/boot/dts/mediatek/mt8183.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -280,6 +280,14 @@ opp2_15: opp-1196000000 { 
		};

	};



	cci: cci {

		compatible = "mediatek,mt8183-cci";

		clocks = <&mcucfg CLK_MCU_BUS_SEL>,

			 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;

		clock-names = "cci", "intermediate";

		operating-points-v2 = <&cci_opp>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;