Commit f0408020 authored by Marijn Suijten's avatar Marijn Suijten Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Take INTF index as parameter in interrupt register defines 



Instead of hardcoding many register defines for every INTF and AD4 index
with a fixed stride, turn the defines into singular chunks of math that
compute the address using the base and this fixed stride multiplied by
the index given as argument to the definitions.

MDP_SSPP_TOP0_OFF is dropped as that constant is zero anyway, and all
register offsets related to it live in dpu_hwio.h.

Suggested-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534221/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-11-27ce1a5ab5c6@somainline.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent d80d7f89

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

+72 −84
Original line number Diff line number Diff line
@@ -17,30 +17,18 @@ 
 * Register offsets in MDSS register file for the interrupt registers

 * w.r.t. the MDP base

 */

#define MDP_SSPP_TOP0_OFF		0x0

#define MDP_INTF_0_OFF			0x6A000

#define MDP_INTF_1_OFF			0x6A800

#define MDP_INTF_2_OFF			0x6B000

#define MDP_INTF_3_OFF			0x6B800

#define MDP_INTF_4_OFF			0x6C000

#define MDP_INTF_5_OFF			0x6C800

#define INTF_INTR_EN			0x1c0

#define INTF_INTR_STATUS		0x1c4

#define INTF_INTR_CLEAR			0x1c8

#define MDP_AD4_0_OFF			0x7C000

#define MDP_AD4_1_OFF			0x7D000

#define MDP_AD4_INTR_EN_OFF		0x41c

#define MDP_AD4_INTR_CLEAR_OFF		0x424

#define MDP_AD4_INTR_STATUS_OFF		0x420

#define MDP_INTF_0_OFF_REV_7xxx		0x34000

#define MDP_INTF_1_OFF_REV_7xxx		0x35000

#define MDP_INTF_2_OFF_REV_7xxx		0x36000

#define MDP_INTF_3_OFF_REV_7xxx		0x37000

#define MDP_INTF_4_OFF_REV_7xxx		0x38000

#define MDP_INTF_5_OFF_REV_7xxx		0x39000

#define MDP_INTF_6_OFF_REV_7xxx		0x3a000

#define MDP_INTF_7_OFF_REV_7xxx		0x3b000

#define MDP_INTF_8_OFF_REV_7xxx		0x3c000

#define MDP_INTF_OFF(intf)				(0x6A000 + 0x800 * (intf))

#define MDP_INTF_INTR_EN(intf)				(MDP_INTF_OFF(intf) + 0x1c0)

#define MDP_INTF_INTR_STATUS(intf)			(MDP_INTF_OFF(intf) + 0x1c4)

#define MDP_INTF_INTR_CLEAR(intf)			(MDP_INTF_OFF(intf) + 0x1c8)

#define MDP_AD4_OFF(ad4)				(0x7C000 + 0x1000 * (ad4))

#define MDP_AD4_INTR_EN_OFF(ad4)			(MDP_AD4_OFF(ad4) + 0x41c)

#define MDP_AD4_INTR_CLEAR_OFF(ad4)			(MDP_AD4_OFF(ad4) + 0x424)

#define MDP_AD4_INTR_STATUS_OFF(ad4)			(MDP_AD4_OFF(ad4) + 0x420)

#define MDP_INTF_REV_7xxx_OFF(intf)			(0x34000 + 0x1000 * (intf))

#define MDP_INTF_REV_7xxx_INTR_EN(intf)			(MDP_INTF_REV_7xxx_OFF(intf) + 0x1c0)

#define MDP_INTF_REV_7xxx_INTR_STATUS(intf)		(MDP_INTF_REV_7xxx_OFF(intf) + 0x1c4)

#define MDP_INTF_REV_7xxx_INTR_CLEAR(intf)		(MDP_INTF_REV_7xxx_OFF(intf) + 0x1c8)



/**

 * struct dpu_intr_reg - array of DPU register sets
@@ -61,104 +49,104 @@ struct dpu_intr_reg { 
 */

static const struct dpu_intr_reg dpu_intr_set[] = {

	[MDP_SSPP_TOP0_INTR] = {

		MDP_SSPP_TOP0_OFF+INTR_CLEAR,

		MDP_SSPP_TOP0_OFF+INTR_EN,

		MDP_SSPP_TOP0_OFF+INTR_STATUS

		INTR_CLEAR,

		INTR_EN,

		INTR_STATUS

	},

	[MDP_SSPP_TOP0_INTR2] = {

		MDP_SSPP_TOP0_OFF+INTR2_CLEAR,

		MDP_SSPP_TOP0_OFF+INTR2_EN,

		MDP_SSPP_TOP0_OFF+INTR2_STATUS

		INTR2_CLEAR,

		INTR2_EN,

		INTR2_STATUS

	},

	[MDP_SSPP_TOP0_HIST_INTR] = {

		MDP_SSPP_TOP0_OFF+HIST_INTR_CLEAR,

		MDP_SSPP_TOP0_OFF+HIST_INTR_EN,

		MDP_SSPP_TOP0_OFF+HIST_INTR_STATUS

		HIST_INTR_CLEAR,

		HIST_INTR_EN,

		HIST_INTR_STATUS

	},

	[MDP_INTF0_INTR] = {

		MDP_INTF_0_OFF+INTF_INTR_CLEAR,

		MDP_INTF_0_OFF+INTF_INTR_EN,

		MDP_INTF_0_OFF+INTF_INTR_STATUS

		MDP_INTF_INTR_CLEAR(0),

		MDP_INTF_INTR_EN(0),

		MDP_INTF_INTR_STATUS(0)

	},

	[MDP_INTF1_INTR] = {

		MDP_INTF_1_OFF+INTF_INTR_CLEAR,

		MDP_INTF_1_OFF+INTF_INTR_EN,

		MDP_INTF_1_OFF+INTF_INTR_STATUS

		MDP_INTF_INTR_CLEAR(1),

		MDP_INTF_INTR_EN(1),

		MDP_INTF_INTR_STATUS(1)

	},

	[MDP_INTF2_INTR] = {

		MDP_INTF_2_OFF+INTF_INTR_CLEAR,

		MDP_INTF_2_OFF+INTF_INTR_EN,

		MDP_INTF_2_OFF+INTF_INTR_STATUS

		MDP_INTF_INTR_CLEAR(2),

		MDP_INTF_INTR_EN(2),

		MDP_INTF_INTR_STATUS(2)

	},

	[MDP_INTF3_INTR] = {

		MDP_INTF_3_OFF+INTF_INTR_CLEAR,

		MDP_INTF_3_OFF+INTF_INTR_EN,

		MDP_INTF_3_OFF+INTF_INTR_STATUS

		MDP_INTF_INTR_CLEAR(3),

		MDP_INTF_INTR_EN(3),

		MDP_INTF_INTR_STATUS(3)

	},

	[MDP_INTF4_INTR] = {

		MDP_INTF_4_OFF+INTF_INTR_CLEAR,

		MDP_INTF_4_OFF+INTF_INTR_EN,

		MDP_INTF_4_OFF+INTF_INTR_STATUS

		MDP_INTF_INTR_CLEAR(4),

		MDP_INTF_INTR_EN(4),

		MDP_INTF_INTR_STATUS(4)

	},

	[MDP_INTF5_INTR] = {

		MDP_INTF_5_OFF+INTF_INTR_CLEAR,

		MDP_INTF_5_OFF+INTF_INTR_EN,

		MDP_INTF_5_OFF+INTF_INTR_STATUS

		MDP_INTF_INTR_CLEAR(5),

		MDP_INTF_INTR_EN(5),

		MDP_INTF_INTR_STATUS(5)

	},

	[MDP_AD4_0_INTR] = {

		MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF,

		MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF,

		MDP_AD4_0_OFF + MDP_AD4_INTR_STATUS_OFF,

		MDP_AD4_INTR_CLEAR_OFF(0),

		MDP_AD4_INTR_EN_OFF(0),

		MDP_AD4_INTR_STATUS_OFF(0),

	},

	[MDP_AD4_1_INTR] = {

		MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF,

		MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF,

		MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF,

		MDP_AD4_INTR_CLEAR_OFF(1),

		MDP_AD4_INTR_EN_OFF(1),

		MDP_AD4_INTR_STATUS_OFF(1),

	},

	[MDP_INTF0_7xxx_INTR] = {

		MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(0),

		MDP_INTF_REV_7xxx_INTR_EN(0),

		MDP_INTF_REV_7xxx_INTR_STATUS(0)

	},

	[MDP_INTF1_7xxx_INTR] = {

		MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(1),

		MDP_INTF_REV_7xxx_INTR_EN(1),

		MDP_INTF_REV_7xxx_INTR_STATUS(1)

	},

	[MDP_INTF2_7xxx_INTR] = {

		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(2),

		MDP_INTF_REV_7xxx_INTR_EN(2),

		MDP_INTF_REV_7xxx_INTR_STATUS(2)

	},

	[MDP_INTF3_7xxx_INTR] = {

		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(3),

		MDP_INTF_REV_7xxx_INTR_EN(3),

		MDP_INTF_REV_7xxx_INTR_STATUS(3)

	},

	[MDP_INTF4_7xxx_INTR] = {

		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(4),

		MDP_INTF_REV_7xxx_INTR_EN(4),

		MDP_INTF_REV_7xxx_INTR_STATUS(4)

	},

	[MDP_INTF5_7xxx_INTR] = {

		MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(5),

		MDP_INTF_REV_7xxx_INTR_EN(5),

		MDP_INTF_REV_7xxx_INTR_STATUS(5)

	},

	[MDP_INTF6_7xxx_INTR] = {

		MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(6),

		MDP_INTF_REV_7xxx_INTR_EN(6),

		MDP_INTF_REV_7xxx_INTR_STATUS(6)

	},

	[MDP_INTF7_7xxx_INTR] = {

		MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(7),

		MDP_INTF_REV_7xxx_INTR_EN(7),

		MDP_INTF_REV_7xxx_INTR_STATUS(7)

	},

	[MDP_INTF8_7xxx_INTR] = {

		MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_STATUS

		MDP_INTF_REV_7xxx_INTR_CLEAR(8),

		MDP_INTF_REV_7xxx_INTR_EN(8),

		MDP_INTF_REV_7xxx_INTR_STATUS(8)

	},

};