Commit d80d7f89 authored by Marijn Suijten's avatar Marijn Suijten Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Sort INTF registers numerically 



A bunch of registers were appended at the end in e.g. commit
91143873 ("drm/msm/dpu: Add MISR register support for interface")
rather than being inserted in a place that maintains numerical sorting:
restore said numerical sorting.

Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534213/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-10-27ce1a5ab5c6@somainline.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent d9388af5

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

+7 −4
Original line number Diff line number Diff line
@@ -36,6 +36,10 @@ 
#define INTF_CONFIG2                    0x060

#define INTF_DISPLAY_DATA_HCTL          0x064

#define INTF_ACTIVE_DATA_HCTL           0x068



#define INTF_DSI_CMD_MODE_TRIGGER_EN    0x084

#define INTF_PANEL_FORMAT               0x090



#define INTF_FRAME_LINE_COUNT_EN        0x0A8

#define INTF_FRAME_COUNT                0x0AC

#define INTF_LINE_COUNT                 0x0B0
@@ -44,8 +48,6 @@ 
#define INTF_DEFLICKER_STRNG_COEFF      0x0F4

#define INTF_DEFLICKER_WEAK_COEFF       0x0F8



#define INTF_DSI_CMD_MODE_TRIGGER_EN    0x084

#define INTF_PANEL_FORMAT               0x090

#define INTF_TPG_ENABLE                 0x100

#define INTF_TPG_MAIN_CONTROL           0x104

#define INTF_TPG_VIDEO_CONFIG           0x108
@@ -57,6 +59,9 @@ 
#define INTF_PROG_FETCH_START           0x170

#define INTF_PROG_ROT_START             0x174



#define INTF_MISR_CTRL                  0x180

#define INTF_MISR_SIGNATURE             0x184



#define INTF_MUX                        0x25C

#define INTF_STATUS                     0x26C
@@ -66,8 +71,6 @@ 
#define INTF_CFG2_DATABUS_WIDEN	BIT(0)

#define INTF_CFG2_DATA_HCTL_EN	BIT(4)



#define INTF_MISR_CTRL			0x180

#define INTF_MISR_SIGNATURE		0x184



static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,

		const struct intf_timing_params *p,