Commit ef7d0e8d authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: inline SSPP_BLK macros 



To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.

Tested-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/545377/
Link: https://lore.kernel.org/r/20230704022136.130522-11-dmitry.baryshkov@linaro.org
parent 2a6387e2

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

+65 −16
Original line number Diff line number Diff line
@@ -71,22 +71,71 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = { 
};



static const struct dpu_sspp_cfg msm8998_sspp[] = {

	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,

		msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),

	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,

		msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),

	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,

		msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),

	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,

		msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),

	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,

		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),

	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,

		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),

	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,

		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),

	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,

		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),

	{

		.name = "sspp_0", .id = SSPP_VIG0,

		.base = 0x4000, .len = 0x1ac,

		.features = VIG_MSM8998_MASK,

		.sblk = &msm8998_vig_sblk_0,

		.xin_id = 0,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG0,

	}, {

		.name = "sspp_1", .id = SSPP_VIG1,

		.base = 0x6000, .len = 0x1ac,

		.features = VIG_MSM8998_MASK,

		.sblk = &msm8998_vig_sblk_1,

		.xin_id = 4,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG1,

	}, {

		.name = "sspp_2", .id = SSPP_VIG2,

		.base = 0x8000, .len = 0x1ac,

		.features = VIG_MSM8998_MASK,

		.sblk = &msm8998_vig_sblk_2,

		.xin_id = 8,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG2,

	}, {

		.name = "sspp_3", .id = SSPP_VIG3,

		.base = 0xa000, .len = 0x1ac,

		.features = VIG_MSM8998_MASK,

		.sblk = &msm8998_vig_sblk_3,

		.xin_id = 12,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG3,

	}, {

		.name = "sspp_8", .id = SSPP_DMA0,

		.base = 0x24000, .len = 0x1ac,

		.features = DMA_MSM8998_MASK,

		.sblk = &sdm845_dma_sblk_0,

		.xin_id = 1,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA0,

	}, {

		.name = "sspp_9", .id = SSPP_DMA1,

		.base = 0x26000, .len = 0x1ac,

		.features = DMA_MSM8998_MASK,

		.sblk = &sdm845_dma_sblk_1,

		.xin_id = 5,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA1,

	}, {

		.name = "sspp_10", .id = SSPP_DMA2,

		.base = 0x28000, .len = 0x1ac,

		.features = DMA_CURSOR_MSM8998_MASK,

		.sblk = &sdm845_dma_sblk_2,

		.xin_id = 9,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA2,

	}, {

		.name = "sspp_11", .id = SSPP_DMA3,

		.base = 0x2a000, .len = 0x1ac,

		.features = DMA_CURSOR_MSM8998_MASK,

		.sblk = &sdm845_dma_sblk_3,

		.xin_id = 13,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA3,

	},

};



static const struct dpu_lm_cfg msm8998_lm[] = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

+65 −16
Original line number Diff line number Diff line
@@ -69,22 +69,71 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = { 
};



static const struct dpu_sspp_cfg sdm845_sspp[] = {

	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA,

		sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),

	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA,

		sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),

	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA,

		sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),

	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA,

		sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),

	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA,

		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),

	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA,

		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),

	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,

		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),

	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,

		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),

	{

		.name = "sspp_0", .id = SSPP_VIG0,

		.base = 0x4000, .len = 0x1c8,

		.features = VIG_SDM845_MASK_SDMA,

		.sblk = &sdm845_vig_sblk_0,

		.xin_id = 0,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG0,

	}, {

		.name = "sspp_1", .id = SSPP_VIG1,

		.base = 0x6000, .len = 0x1c8,

		.features = VIG_SDM845_MASK_SDMA,

		.sblk = &sdm845_vig_sblk_1,

		.xin_id = 4,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG1,

	}, {

		.name = "sspp_2", .id = SSPP_VIG2,

		.base = 0x8000, .len = 0x1c8,

		.features = VIG_SDM845_MASK_SDMA,

		.sblk = &sdm845_vig_sblk_2,

		.xin_id = 8,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG2,

	}, {

		.name = "sspp_3", .id = SSPP_VIG3,

		.base = 0xa000, .len = 0x1c8,

		.features = VIG_SDM845_MASK_SDMA,

		.sblk = &sdm845_vig_sblk_3,

		.xin_id = 12,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG3,

	}, {

		.name = "sspp_8", .id = SSPP_DMA0,

		.base = 0x24000, .len = 0x1c8,

		.features = DMA_SDM845_MASK_SDMA,

		.sblk = &sdm845_dma_sblk_0,

		.xin_id = 1,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA0,

	}, {

		.name = "sspp_9", .id = SSPP_DMA1,

		.base = 0x26000, .len = 0x1c8,

		.features = DMA_SDM845_MASK_SDMA,

		.sblk = &sdm845_dma_sblk_1,

		.xin_id = 5,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA1,

	}, {

		.name = "sspp_10", .id = SSPP_DMA2,

		.base = 0x28000, .len = 0x1c8,

		.features = DMA_CURSOR_SDM845_MASK_SDMA,

		.sblk = &sdm845_dma_sblk_2,

		.xin_id = 9,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA2,

	}, {

		.name = "sspp_11", .id = SSPP_DMA3,

		.base = 0x2a000, .len = 0x1c8,

		.features = DMA_CURSOR_SDM845_MASK_SDMA,

		.sblk = &sdm845_dma_sblk_3,

		.xin_id = 13,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA3,

	},

};



static const struct dpu_lm_cfg sdm845_lm[] = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

+65 −16
Original line number Diff line number Diff line
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { 
};



static const struct dpu_sspp_cfg sm8150_sspp[] = {

	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,

		sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),

	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,

		sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),

	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,

		sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),

	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,

		sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),

	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,

		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),

	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,

		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),

	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,

		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),

	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,

		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),

	{

		.name = "sspp_0", .id = SSPP_VIG0,

		.base = 0x4000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &sdm845_vig_sblk_0,

		.xin_id = 0,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG0,

	}, {

		.name = "sspp_1", .id = SSPP_VIG1,

		.base = 0x6000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &sdm845_vig_sblk_1,

		.xin_id = 4,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG1,

	}, {

		.name = "sspp_2", .id = SSPP_VIG2,

		.base = 0x8000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &sdm845_vig_sblk_2,

		.xin_id = 8,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG2,

	}, {

		.name = "sspp_3", .id = SSPP_VIG3,

		.base = 0xa000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &sdm845_vig_sblk_3,

		.xin_id = 12,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG3,

	}, {

		.name = "sspp_8", .id = SSPP_DMA0,

		.base = 0x24000, .len = 0x1f0,

		.features = DMA_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_0,

		.xin_id = 1,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA0,

	}, {

		.name = "sspp_9", .id = SSPP_DMA1,

		.base = 0x26000, .len = 0x1f0,

		.features = DMA_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_1,

		.xin_id = 5,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA1,

	}, {

		.name = "sspp_10", .id = SSPP_DMA2,

		.base = 0x28000, .len = 0x1f0,

		.features = DMA_CURSOR_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_2,

		.xin_id = 9,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA2,

	}, {

		.name = "sspp_11", .id = SSPP_DMA3,

		.base = 0x2a000, .len = 0x1f0,

		.features = DMA_CURSOR_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_3,

		.xin_id = 13,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA3,

	},

};



static const struct dpu_lm_cfg sm8150_lm[] = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

+65 −16
Original line number Diff line number Diff line
@@ -77,22 +77,71 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = { 
};



static const struct dpu_sspp_cfg sc8180x_sspp[] = {

	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,

		sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),

	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,

		sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),

	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,

		sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),

	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,

		sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),

	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,

		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),

	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,

		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),

	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,

		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),

	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,

		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),

	{

		.name = "sspp_0", .id = SSPP_VIG0,

		.base = 0x4000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &sdm845_vig_sblk_0,

		.xin_id = 0,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG0,

	}, {

		.name = "sspp_1", .id = SSPP_VIG1,

		.base = 0x6000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &sdm845_vig_sblk_1,

		.xin_id = 4,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG1,

	}, {

		.name = "sspp_2", .id = SSPP_VIG2,

		.base = 0x8000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &sdm845_vig_sblk_2,

		.xin_id = 8,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG2,

	}, {

		.name = "sspp_3", .id = SSPP_VIG3,

		.base = 0xa000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &sdm845_vig_sblk_3,

		.xin_id = 12,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG3,

	}, {

		.name = "sspp_8", .id = SSPP_DMA0,

		.base = 0x24000, .len = 0x1f0,

		.features = DMA_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_0,

		.xin_id = 1,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA0,

	}, {

		.name = "sspp_9", .id = SSPP_DMA1,

		.base = 0x26000, .len = 0x1f0,

		.features = DMA_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_1,

		.xin_id = 5,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA1,

	}, {

		.name = "sspp_10", .id = SSPP_DMA2,

		.base = 0x28000, .len = 0x1f0,

		.features = DMA_CURSOR_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_2,

		.xin_id = 9,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA2,

	}, {

		.name = "sspp_11", .id = SSPP_DMA3,

		.base = 0x2a000, .len = 0x1f0,

		.features = DMA_CURSOR_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_3,

		.xin_id = 13,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA3,

	},

};



static const struct dpu_lm_cfg sc8180x_lm[] = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

+65 −16
Original line number Diff line number Diff line
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = { 
};



static const struct dpu_sspp_cfg sm8250_sspp[] = {

	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,

		sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),

	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA,

		sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),

	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA,

		sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),

	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA,

		sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),

	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,

		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),

	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA,

		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),

	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,

		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),

	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,

		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),

	{

		.name = "sspp_0", .id = SSPP_VIG0,

		.base = 0x4000, .len = 0x1f8,

		.features = VIG_SC7180_MASK_SDMA,

		.sblk = &sm8250_vig_sblk_0,

		.xin_id = 0,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG0,

	}, {

		.name = "sspp_1", .id = SSPP_VIG1,

		.base = 0x6000, .len = 0x1f8,

		.features = VIG_SC7180_MASK_SDMA,

		.sblk = &sm8250_vig_sblk_1,

		.xin_id = 4,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG1,

	}, {

		.name = "sspp_2", .id = SSPP_VIG2,

		.base = 0x8000, .len = 0x1f8,

		.features = VIG_SC7180_MASK_SDMA,

		.sblk = &sm8250_vig_sblk_2,

		.xin_id = 8,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG2,

	}, {

		.name = "sspp_3", .id = SSPP_VIG3,

		.base = 0xa000, .len = 0x1f8,

		.features = VIG_SC7180_MASK_SDMA,

		.sblk = &sm8250_vig_sblk_3,

		.xin_id = 12,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG3,

	}, {

		.name = "sspp_8", .id = SSPP_DMA0,

		.base = 0x24000, .len = 0x1f8,

		.features = DMA_SDM845_MASK_SDMA,

		.sblk = &sdm845_dma_sblk_0,

		.xin_id = 1,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA0,

	}, {

		.name = "sspp_9", .id = SSPP_DMA1,

		.base = 0x26000, .len = 0x1f8,

		.features = DMA_SDM845_MASK_SDMA,

		.sblk = &sdm845_dma_sblk_1,

		.xin_id = 5,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA1,

	}, {

		.name = "sspp_10", .id = SSPP_DMA2,

		.base = 0x28000, .len = 0x1f8,

		.features = DMA_CURSOR_SDM845_MASK_SDMA,

		.sblk = &sdm845_dma_sblk_2,

		.xin_id = 9,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA2,

	}, {

		.name = "sspp_11", .id = SSPP_DMA3,

		.base = 0x2a000, .len = 0x1f8,

		.features = DMA_CURSOR_SDM845_MASK_SDMA,

		.sblk = &sdm845_dma_sblk_3,

		.xin_id = 13,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA3,

	},

};



static const struct dpu_lm_cfg sm8250_lm[] = {