Commit 2a6387e2 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: correct indentation for CTL definitions 



Shift dpu_ctl_cfg contents to correct the indentation of CTL blocks.
This is done in preparation to expanding the rest of hardware block
defines, so that all blocks have similar indentation.

Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Tested-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/545374/
Link: https://lore.kernel.org/r/20230704022136.130522-10-dmitry.baryshkov@linaro.org
parent 038c06bd

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

+21 −25
Original line number Diff line number Diff line
@@ -50,24 +50,20 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = { 
		.base = 0x1000, .len = 0x94,

		.features = BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	},

	{

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x94,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	},

	{

	}, {

		.name = "ctl_2", .id = CTL_2,

		.base = 0x1400, .len = 0x94,

		.features = BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	},

	{

	}, {

		.name = "ctl_3", .id = CTL_3,

		.base = 0x1600, .len = 0x94,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	},

	{

	}, {

		.name = "ctl_4", .id = CTL_4,

		.base = 0x1800, .len = 0x94,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

+21 −25
Original line number Diff line number Diff line
@@ -48,24 +48,20 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = { 
		.base = 0x1000, .len = 0xe4,

		.features = BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	},

	{

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0xe4,

		.features = BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	},

	{

	}, {

		.name = "ctl_2", .id = CTL_2,

		.base = 0x1400, .len = 0xe4,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	},

	{

	}, {

		.name = "ctl_3", .id = CTL_3,

		.base = 0x1600, .len = 0xe4,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	},

	{

	}, {

		.name = "ctl_4", .id = CTL_4,

		.base = 0x1800, .len = 0xe4,

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

+29 −34
Original line number Diff line number Diff line
@@ -49,32 +49,27 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { 
		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	},

	{

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	},

	{

	}, {

		.name = "ctl_2", .id = CTL_2,

		.base = 0x1400, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	},

	{

	}, {

		.name = "ctl_3", .id = CTL_3,

		.base = 0x1600, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	},

	{

	}, {

		.name = "ctl_4", .id = CTL_4,

		.base = 0x1800, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

	},

	{

	}, {

		.name = "ctl_5", .id = CTL_5,

		.base = 0x1a00, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

+29 −34
Original line number Diff line number Diff line
@@ -48,32 +48,27 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = { 
		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	},

	{

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	},

	{

	}, {

		.name = "ctl_2", .id = CTL_2,

		.base = 0x1400, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	},

	{

	}, {

		.name = "ctl_3", .id = CTL_3,

		.base = 0x1600, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	},

	{

	}, {

		.name = "ctl_4", .id = CTL_4,

		.base = 0x1800, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

	},

	{

	}, {

		.name = "ctl_5", .id = CTL_5,

		.base = 0x1a00, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

+29 −34
Original line number Diff line number Diff line
@@ -49,32 +49,27 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = { 
		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	},

	{

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	},

	{

	}, {

		.name = "ctl_2", .id = CTL_2,

		.base = 0x1400, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	},

	{

	}, {

		.name = "ctl_3", .id = CTL_3,

		.base = 0x1600, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	},

	{

	}, {

		.name = "ctl_4", .id = CTL_4,

		.base = 0x1800, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

	},

	{

	}, {

		.name = "ctl_5", .id = CTL_5,

		.base = 0x1a00, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),