Unverified Commit e035ddb6 authored Oct 23, 2023 by Krzysztof Kozlowski Committed by Arnd Bergmann Oct 23, 2023

arm64: dts: socionext: add missing cache properties

As all level 2 and level 3 caches are unified, add required
cache-unified property to fix warnings like:

uniphier-ld11-ref.dtb: l2-cache: 'cache-unified' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20231023021221.2884828-3-hayashi.kunihiko@socionext.com

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parent 0804f3be

arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -53,6 +53,7 @@ cpu1: cpu@1 {
		l2: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -87,11 +87,13 @@ cpu3: cpu@101 {
		a72_l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		a53_l2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -84,6 +84,7 @@ cpu3: cpu@3 {
		l2: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};