Commit c2f76057 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'ti-k3-dt-for-v5.12' of... 

Merge tag 'ti-k3-dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt

Devicetree changes for TI K3 platforms for v5.12 merge window:

- Common fixups: PMU compatible, MMC dtbs_check warnings squelch

- J7200: R5F, PCIe, SERDES support

- J721E: PCIE fixups

* tag 'ti-k3-dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux:
  arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
  arm64: dts: ti: k3: mmc: fix dtbs_check warnings
  arm64: dts: ti: k3-j7200-som-p0: Add DDR carveout memory nodes for R5Fs
  arm64: dts: ti: k3-j7200-som-p0: Add mailboxes to R5Fs
  arm64: dts: ti: k3-j7200: Add R5F cluster nodes
  arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe
  arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0
  arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
  arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
  arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl
  arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions

Link: https://lore.kernel.org/r/20210130131422.yvq2edxfongys7x5@pendant


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7d1734cf ae10ce93

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ main_spi4: spi@2140000 { 
		#size-cells = <0>;

	};



	sdhci0: sdhci@4f80000 {

	sdhci0: mmc@4f80000 {

		compatible = "ti,am654-sdhci-5.1";

		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;

		power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
@@ -280,7 +280,7 @@ sdhci0: sdhci@4f80000 { 
		dma-coherent;

	};



	sdhci1: sdhci@4fa0000 {

	sdhci1: mmc@4fa0000 {

		compatible = "ti,am654-sdhci-5.1";

		reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;

		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;

arch/arm64/boot/dts/ti/k3-am65.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 { 
	};



	pmu: pmu {

		compatible = "arm,armv8-pmuv3";

		compatible = "arm,cortex-a53-pmu";

		/* Recommendation from GIC500 TRM Table A.3 */

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};

arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

+38 −0
Original line number Diff line number Diff line
@@ -6,8 +6,10 @@ 
/dts-v1/;



#include "k3-j7200-som-p0.dtsi"

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/net/ti-dp83867.h>

#include <dt-bindings/mux/ti-serdes.h>

#include <dt-bindings/phy/phy.h>



/ {

	chosen {
@@ -218,3 +220,39 @@ adc { 
		ti,adc-channels = <0 1 2 3 4 5 6 7>;

	};

};



&serdes_refclk {

	clock-frequency = <100000000>;

};



&serdes0 {

	serdes0_pcie_link: phy@0 {

		reg = <0>;

		cdns,num-lanes = <2>;

		#phy-cells = <0>;

		cdns,phy-type = <PHY_TYPE_PCIE>;

		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;

	};



	serdes0_qsgmii_link: phy@1 {

		reg = <2>;

		cdns,num-lanes = <1>;

		#phy-cells = <0>;

		cdns,phy-type = <PHY_TYPE_QSGMII>;

		resets = <&serdes_wiz0 3>;

	};

};



&pcie1_rc {

	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;

	phys = <&serdes0_pcie_link>;

	phy-names = "pcie-phy";

	num-lanes = <2>;

};



&pcie1_ep {

	phys = <&serdes0_pcie_link>;

	phy-names = "pcie-phy";

	num-lanes = <2>;

	status = "disabled";

};

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

+156 −5
Original line number Diff line number Diff line
@@ -2,9 +2,16 @@ 
/*

 * Device Tree Source for J7200 SoC Family Main Domain peripherals

 *

 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/

 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/

 */



/ {

	serdes_refclk: serdes-refclk {

		#clock-cells = <0>;

		compatible = "fixed-clock";

	};

};



&cbass_main {

	msmc_ram: sram@70000000 {

		compatible = "mmio-sram";
@@ -499,8 +506,8 @@ main_sdhci0: mmc@4f80000 { 
		reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;

		clock-names = "clk_xin", "clk_ahb";

		clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;

		clock-names = "clk_ahb", "clk_xin";

		clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-mmc-hs = <0x0>;

		ti,otap-del-sel-ddr52 = <0x6>;
@@ -518,8 +525,8 @@ main_sdhci1: mmc@4fb0000 { 
		reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;

		clock-names = "clk_xin", "clk_ahb";

		clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;

		clock-names = "clk_ahb", "clk_xin";

		clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-sd-hs = <0x0>;

		ti,otap-del-sel-sdr12 = <0xf>;
@@ -531,6 +538,110 @@ main_sdhci1: mmc@4fb0000 { 
		dma-coherent;

	};



	serdes_wiz0: wiz@5060000 {

		compatible = "ti,j721e-wiz-10g";

		#address-cells = <1>;

		#size-cells = <1>;

		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;

		clock-names = "fck", "core_ref_clk", "ext_ref_clk";

		num-lanes = <4>;

		#reset-cells = <1>;

		ranges = <0x5060000 0x0 0x5060000 0x10000>;



		assigned-clocks = <&k3_clks 292 85>;

		assigned-clock-parents = <&k3_clks 292 89>;



		wiz0_pll0_refclk: pll0-refclk {

			clocks = <&k3_clks 292 85>, <&serdes_refclk>;

			clock-output-names = "wiz0_pll0_refclk";

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_pll0_refclk>;

			assigned-clock-parents = <&k3_clks 292 85>;

		};



		wiz0_pll1_refclk: pll1-refclk {

			clocks = <&k3_clks 292 85>, <&serdes_refclk>;

			clock-output-names = "wiz0_pll1_refclk";

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_pll1_refclk>;

			assigned-clock-parents = <&k3_clks 292 85>;

		};



		wiz0_refclk_dig: refclk-dig {

			clocks = <&k3_clks 292 85>, <&serdes_refclk>;

			clock-output-names = "wiz0_refclk_dig";

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_refclk_dig>;

			assigned-clock-parents = <&k3_clks 292 85>;

		};



		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {

			clocks = <&wiz0_refclk_dig>;

			#clock-cells = <0>;

		};



		serdes0: serdes@5060000 {

			compatible = "ti,j721e-serdes-10g";

			reg = <0x05060000 0x00010000>;

			reg-names = "torrent_phy";

			resets = <&serdes_wiz0 0>;

			reset-names = "torrent_reset";

			clocks = <&wiz0_pll0_refclk>;

			clock-names = "refclk";

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	pcie1_rc: pcie@2910000 {

		compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";

		reg = <0x00 0x02910000 0x00 0x1000>,

		      <0x00 0x02917000 0x00 0x400>,

		      <0x00 0x0d800000 0x00 0x00800000>,

		      <0x00 0x18000000 0x00 0x00001000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;

		device_type = "pci";

		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;

		max-link-speed = <3>;

		num-lanes = <4>;

		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 240 6>;

		clock-names = "fck";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xf>;

		cdns,no-bar-match-nbits = <64>;

		vendor-id = /bits/ 16 <0x104c>;

		device-id = /bits/ 16 <0xb00f>;

		msi-map = <0x0 &gic_its 0x0 0x10000>;

		dma-coherent;

		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,

			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

	};



	pcie1_ep: pcie-ep@2910000 {

		compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";

		reg = <0x00 0x02910000 0x00 0x1000>,

		      <0x00 0x02917000 0x00 0x400>,

		      <0x00 0x0d800000 0x00 0x00800000>,

		      <0x00 0x18000000 0x00 0x08000000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "mem";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;

		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;

		max-link-speed = <3>;

		num-lanes = <4>;

		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 240 6>;

		clock-names = "fck";

		max-functions = /bits/ 8 <6>;

		dma-coherent;

	};



	usbss0: cdns-usb@4104000 {

		compatible = "ti,j721e-usb";

		reg = <0x00 0x4104000 0x00 0x100>;
@@ -560,4 +671,44 @@ usb0: usb@6000000 { 
			dr_mode = "otg";

		};

	};



	main_r5fss0: r5fss@5c00000 {

		compatible = "ti,j7200-r5fss";

		ti,cluster-mode = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,

			 <0x5d00000 0x00 0x5d00000 0x20000>;

		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;



		main_r5fss0_core0: r5f@5c00000 {

			compatible = "ti,j7200-r5f";

			reg = <0x5c00000 0x00010000>,

			      <0x5c10000 0x00010000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <245>;

			ti,sci-proc-ids = <0x06 0xff>;

			resets = <&k3_reset 245 1>;

			firmware-name = "j7200-main-r5f0_0-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};



		main_r5fss0_core1: r5f@5d00000 {

			compatible = "ti,j7200-r5f";

			reg = <0x5d00000 0x00008000>,

			      <0x5d10000 0x00008000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <246>;

			ti,sci-proc-ids = <0x07 0xff>;

			resets = <&k3_reset 246 1>;

			firmware-name = "j7200-main-r5f0_1-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};

	};

};

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

+41 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals

 *

 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/

 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/

 */



&cbass_mcu_wakeup {
@@ -289,4 +289,44 @@ adc { 
			compatible = "ti,am3359-adc";

		};

	};



	mcu_r5fss0: r5fss@41000000 {

		compatible = "ti,j7200-r5fss";

		ti,cluster-mode = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x41000000 0x00 0x41000000 0x20000>,

			 <0x41400000 0x00 0x41400000 0x20000>;

		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;



		mcu_r5fss0_core0: r5f@41000000 {

			compatible = "ti,j7200-r5f";

			reg = <0x41000000 0x00010000>,

			      <0x41010000 0x00010000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <250>;

			ti,sci-proc-ids = <0x01 0xff>;

			resets = <&k3_reset 250 1>;

			firmware-name = "j7200-mcu-r5f0_0-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};



		mcu_r5fss0_core1: r5f@41400000 {

			compatible = "ti,j7200-r5f";

			reg = <0x41400000 0x00008000>,

			      <0x41410000 0x00008000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <251>;

			ti,sci-proc-ids = <0x02 0xff>;

			resets = <&k3_reset 251 1>;

			firmware-name = "j7200-mcu-r5f0_1-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};

	};

};