Commit ae10ce93 authored by Nishanth Menon's avatar Nishanth Menon
Browse files

arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific 



We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.

Reported-by: default avatarSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Tested-by: default avatarSuman Anna <s-anna@ti.com>
Reviewed-by: default avatarTero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210120195145.32259-1-nm@ti.com
parent 0cf73209

arch/arm64/boot/dts/ti/k3-am65.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 { 
	};



	pmu: pmu {

		compatible = "arm,armv8-pmuv3";

		compatible = "arm,cortex-a53-pmu";

		/* Recommendation from GIC500 TRM Table A.3 */

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};

arch/arm64/boot/dts/ti/k3-j7200.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ a72_timer0: timer-cl0-cpu0 { 
	};



	pmu: pmu {

		compatible = "arm,armv8-pmuv3";

		compatible = "arm,cortex-a72-pmu";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};

arch/arm64/boot/dts/ti/k3-j721e.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ a72_timer0: timer-cl0-cpu0 { 
	};



	pmu: pmu {

		compatible = "arm,armv8-pmuv3";

		compatible = "arm,cortex-a72-pmu";

		/* Recommendation from GIC500 TRM Table A.3 */

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};