Loading drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +24 −18 Original line number Diff line number Diff line Loading @@ -76,8 +76,10 @@ nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, static int nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) { struct nvkm_therm *therm = nvkm_therm(clk); struct nvkm_volt *volt = nvkm_volt(clk); struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_device *device = subdev->device; struct nvkm_therm *therm = device->therm; struct nvkm_volt *volt = device->volt; struct nvkm_cstate *cstate; int ret; Loading @@ -90,7 +92,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) if (therm) { ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1); if (ret && ret != -ENODEV) { nv_error(clk, "failed to raise fan speed: %d\n", ret); nvkm_error(subdev, "failed to raise fan speed: %d\n", ret); return ret; } } Loading @@ -98,7 +100,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) if (volt) { ret = volt->set_id(volt, cstate->voltage, +1); if (ret && ret != -ENODEV) { nv_error(clk, "failed to raise voltage: %d\n", ret); nvkm_error(subdev, "failed to raise voltage: %d\n", ret); return ret; } } Loading @@ -112,13 +114,13 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) if (volt) { ret = volt->set_id(volt, cstate->voltage, -1); if (ret && ret != -ENODEV) nv_error(clk, "failed to lower voltage: %d\n", ret); nvkm_error(subdev, "failed to lower voltage: %d\n", ret); } if (therm) { ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1); if (ret && ret != -ENODEV) nv_error(clk, "failed to lower fan speed: %d\n", ret); nvkm_error(subdev, "failed to lower fan speed: %d\n", ret); } return ret; Loading Loading @@ -171,7 +173,8 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) static int nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) { struct nvkm_fb *fb = nvkm_fb(clk); struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_fb *fb = subdev->device->fb; struct nvkm_pstate *pstate; int ret, idx = 0; Loading @@ -180,7 +183,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) break; } nv_debug(clk, "setting performance state %d\n", pstatei); nvkm_debug(subdev, "setting performance state %d\n", pstatei); clk->pstate = pstatei; if (fb->ram && fb->ram->calc) { Loading @@ -200,13 +203,14 @@ static void nvkm_pstate_work(struct work_struct *work) { struct nvkm_clk *clk = container_of(work, typeof(*clk), work); struct nvkm_subdev *subdev = &clk->subdev; int pstate; if (!atomic_xchg(&clk->waiting, 0)) return; clk->pwrsrc = power_supply_is_system_supplied(); nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, clk->astate, clk->tstate, clk->dstate); Loading @@ -219,11 +223,11 @@ nvkm_pstate_work(struct work_struct *work) pstate = clk->pstate = -1; } nv_trace(clk, "-> %d\n", pstate); nvkm_trace(subdev, "-> %d\n", pstate); if (pstate != clk->pstate) { int ret = nvkm_pstate_prog(clk, pstate); if (ret) { nv_error(clk, "error setting pstate %d: %d\n", nvkm_error(subdev, "error setting pstate %d: %d\n", pstate, ret); } } Loading @@ -247,6 +251,7 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) { struct nvkm_domain *clock = clk->domains - 1; struct nvkm_cstate *cstate; struct nvkm_subdev *subdev = &clk->subdev; char info[3][32] = { "", "", "" }; char name[4] = "--"; int i = -1; Loading @@ -260,12 +265,12 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) if (hi == 0) continue; nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo); nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo); list_for_each_entry(cstate, &pstate->list, head) { u32 freq = cstate->domain[clock->name]; lo = min(lo, freq); hi = max(hi, freq); nv_debug(clk, "%10d KHz\n", freq); nvkm_debug(subdev, "%10d KHz\n", freq); } if (clock->mname && ++i < ARRAY_SIZE(info)) { Loading @@ -281,7 +286,7 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) } } nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]); nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]); } static void Loading Loading @@ -481,6 +486,7 @@ int _nvkm_clk_init(struct nvkm_object *object) { struct nvkm_clk *clk = (void *)object; struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_domain *clock = clk->domains; int ret; Loading @@ -495,7 +501,7 @@ _nvkm_clk_init(struct nvkm_object *object) while (clock->name != nv_clk_src_max) { ret = clk->read(clk, clock->name); if (ret < 0) { nv_error(clk, "%02x freq unknown\n", clock->name); nvkm_error(subdev, "%02x freq unknown\n", clock->name); return ret; } clk->bstate.base.domain[clock->name] = ret; Loading drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +3 −2 Original line number Diff line number Diff line Loading @@ -149,7 +149,8 @@ static int gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) { struct gf100_clk *clk = container_of(obj, typeof(*clk), base); struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; switch (src) { case nv_clk_src_crystal: Loading Loading @@ -191,7 +192,7 @@ gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) case nv_clk_src_vdec: return read_clk(clk, 0x0e); default: nv_error(clk, "invalid clock source %d\n", src); nvkm_error(subdev, "invalid clock source %d\n", src); return -EINVAL; } } Loading drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c +3 −2 Original line number Diff line number Diff line Loading @@ -188,7 +188,8 @@ static int gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) { struct gk104_clk *clk = container_of(obj, typeof(*clk), base); struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; switch (src) { case nv_clk_src_crystal: Loading @@ -212,7 +213,7 @@ gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) case nv_clk_src_vdec: return read_clk(clk, 0x0e); default: nv_error(clk, "invalid clock source %d\n", src); nvkm_error(subdev, "invalid clock source %d\n", src); return -EINVAL; } } Loading drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c +24 −16 Original line number Diff line number Diff line Loading @@ -151,6 +151,7 @@ gk20a_pllg_calc_rate(struct gk20a_clk *clk) static int gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) { struct nvkm_subdev *subdev = &clk->base.subdev; u32 target_clk_f, ref_clk_f, target_freq; u32 min_vco_f, max_vco_f; u32 low_pl, high_pl, best_pl; Loading Loading @@ -198,7 +199,7 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) } } nv_debug(clk, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); /* Select lowest possible VCO */ Loading Loading @@ -249,7 +250,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) WARN_ON(best_delta == ~0); if (best_delta != 0) nv_debug(clk, "no best match for target @ %dMHz on gpc_pll", nvkm_debug(subdev, "no best match for target @ %dMHz on gpc_pll", target_clk_f); clk->m = best_m; Loading @@ -258,7 +260,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) target_freq = gk20a_pllg_calc_rate(clk) / MHZ; nv_debug(clk, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", nvkm_debug(subdev, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]); return 0; } Loading @@ -266,7 +269,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) static int gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) { struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; u32 val; int ramp_timeout; Loading Loading @@ -314,7 +318,7 @@ gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); if (ramp_timeout <= 0) { nv_error(clk, "gpcpll dynamic ramp timeout\n"); nvkm_error(subdev, "gpcpll dynamic ramp timeout\n"); return -ETIMEDOUT; } Loading @@ -340,7 +344,8 @@ _gk20a_pllg_disable(struct gk20a_clk *clk) static int _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) { struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; u32 val, cfg; u32 m_old, pl_old, n_lo; Loading Loading @@ -387,8 +392,8 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) _gk20a_pllg_disable(clk); nv_debug(clk, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n, clk->pl); nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n, clk->pl); n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, clk->parent_rate / MHZ); Loading Loading @@ -567,7 +572,8 @@ static int gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) { struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; switch (src) { case nv_clk_src_crystal: Loading @@ -576,7 +582,7 @@ gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) gk20a_pllg_read_mnp(clk); return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; default: nv_error(clk, "invalid clock source %d\n", src); nvkm_error(subdev, "invalid clock source %d\n", src); return -EINVAL; } } Loading Loading @@ -620,7 +626,8 @@ static int gk20a_clk_init(struct nvkm_object *object) { struct gk20a_clk *clk = (void *)object; struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; int ret; nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); Loading @@ -631,7 +638,7 @@ gk20a_clk_init(struct nvkm_object *object) ret = gk20a_clk_prog(&clk->base); if (ret) { nv_error(clk, "cannot initialize clock\n"); nvkm_error(subdev, "cannot initialize clock\n"); return ret; } Loading Loading @@ -665,7 +672,8 @@ gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, plat = nv_device_to_platform(nv_device(parent)); clk->parent_rate = clk_get_rate(plat->gpu->clk); nv_info(clk, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ); nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ); clk->base.read = gk20a_clk_read; clk->base.calc = gk20a_clk_calc; Loading drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +4 −3 Original line number Diff line number Diff line Loading @@ -139,7 +139,8 @@ static int gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) { struct gt215_clk *clk = container_of(obj, typeof(*clk), base); struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; u32 hsrc; switch (src) { Loading Loading @@ -167,11 +168,11 @@ gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) case 3: return 277000; default: nv_error(clk, "unknown HOST clock source %d\n", hsrc); nvkm_error(subdev, "unknown HOST clock source %d\n", hsrc); return -EINVAL; } default: nv_error(clk, "invalid clock source %d\n", src); nvkm_error(subdev, "invalid clock source %d\n", src); return -EINVAL; } Loading Loading
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +24 −18 Original line number Diff line number Diff line Loading @@ -76,8 +76,10 @@ nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, static int nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) { struct nvkm_therm *therm = nvkm_therm(clk); struct nvkm_volt *volt = nvkm_volt(clk); struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_device *device = subdev->device; struct nvkm_therm *therm = device->therm; struct nvkm_volt *volt = device->volt; struct nvkm_cstate *cstate; int ret; Loading @@ -90,7 +92,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) if (therm) { ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1); if (ret && ret != -ENODEV) { nv_error(clk, "failed to raise fan speed: %d\n", ret); nvkm_error(subdev, "failed to raise fan speed: %d\n", ret); return ret; } } Loading @@ -98,7 +100,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) if (volt) { ret = volt->set_id(volt, cstate->voltage, +1); if (ret && ret != -ENODEV) { nv_error(clk, "failed to raise voltage: %d\n", ret); nvkm_error(subdev, "failed to raise voltage: %d\n", ret); return ret; } } Loading @@ -112,13 +114,13 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) if (volt) { ret = volt->set_id(volt, cstate->voltage, -1); if (ret && ret != -ENODEV) nv_error(clk, "failed to lower voltage: %d\n", ret); nvkm_error(subdev, "failed to lower voltage: %d\n", ret); } if (therm) { ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1); if (ret && ret != -ENODEV) nv_error(clk, "failed to lower fan speed: %d\n", ret); nvkm_error(subdev, "failed to lower fan speed: %d\n", ret); } return ret; Loading Loading @@ -171,7 +173,8 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) static int nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) { struct nvkm_fb *fb = nvkm_fb(clk); struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_fb *fb = subdev->device->fb; struct nvkm_pstate *pstate; int ret, idx = 0; Loading @@ -180,7 +183,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) break; } nv_debug(clk, "setting performance state %d\n", pstatei); nvkm_debug(subdev, "setting performance state %d\n", pstatei); clk->pstate = pstatei; if (fb->ram && fb->ram->calc) { Loading @@ -200,13 +203,14 @@ static void nvkm_pstate_work(struct work_struct *work) { struct nvkm_clk *clk = container_of(work, typeof(*clk), work); struct nvkm_subdev *subdev = &clk->subdev; int pstate; if (!atomic_xchg(&clk->waiting, 0)) return; clk->pwrsrc = power_supply_is_system_supplied(); nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, clk->astate, clk->tstate, clk->dstate); Loading @@ -219,11 +223,11 @@ nvkm_pstate_work(struct work_struct *work) pstate = clk->pstate = -1; } nv_trace(clk, "-> %d\n", pstate); nvkm_trace(subdev, "-> %d\n", pstate); if (pstate != clk->pstate) { int ret = nvkm_pstate_prog(clk, pstate); if (ret) { nv_error(clk, "error setting pstate %d: %d\n", nvkm_error(subdev, "error setting pstate %d: %d\n", pstate, ret); } } Loading @@ -247,6 +251,7 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) { struct nvkm_domain *clock = clk->domains - 1; struct nvkm_cstate *cstate; struct nvkm_subdev *subdev = &clk->subdev; char info[3][32] = { "", "", "" }; char name[4] = "--"; int i = -1; Loading @@ -260,12 +265,12 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) if (hi == 0) continue; nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo); nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo); list_for_each_entry(cstate, &pstate->list, head) { u32 freq = cstate->domain[clock->name]; lo = min(lo, freq); hi = max(hi, freq); nv_debug(clk, "%10d KHz\n", freq); nvkm_debug(subdev, "%10d KHz\n", freq); } if (clock->mname && ++i < ARRAY_SIZE(info)) { Loading @@ -281,7 +286,7 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) } } nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]); nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]); } static void Loading Loading @@ -481,6 +486,7 @@ int _nvkm_clk_init(struct nvkm_object *object) { struct nvkm_clk *clk = (void *)object; struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_domain *clock = clk->domains; int ret; Loading @@ -495,7 +501,7 @@ _nvkm_clk_init(struct nvkm_object *object) while (clock->name != nv_clk_src_max) { ret = clk->read(clk, clock->name); if (ret < 0) { nv_error(clk, "%02x freq unknown\n", clock->name); nvkm_error(subdev, "%02x freq unknown\n", clock->name); return ret; } clk->bstate.base.domain[clock->name] = ret; Loading
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +3 −2 Original line number Diff line number Diff line Loading @@ -149,7 +149,8 @@ static int gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) { struct gf100_clk *clk = container_of(obj, typeof(*clk), base); struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; switch (src) { case nv_clk_src_crystal: Loading Loading @@ -191,7 +192,7 @@ gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) case nv_clk_src_vdec: return read_clk(clk, 0x0e); default: nv_error(clk, "invalid clock source %d\n", src); nvkm_error(subdev, "invalid clock source %d\n", src); return -EINVAL; } } Loading
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c +3 −2 Original line number Diff line number Diff line Loading @@ -188,7 +188,8 @@ static int gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) { struct gk104_clk *clk = container_of(obj, typeof(*clk), base); struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; switch (src) { case nv_clk_src_crystal: Loading @@ -212,7 +213,7 @@ gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) case nv_clk_src_vdec: return read_clk(clk, 0x0e); default: nv_error(clk, "invalid clock source %d\n", src); nvkm_error(subdev, "invalid clock source %d\n", src); return -EINVAL; } } Loading
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c +24 −16 Original line number Diff line number Diff line Loading @@ -151,6 +151,7 @@ gk20a_pllg_calc_rate(struct gk20a_clk *clk) static int gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) { struct nvkm_subdev *subdev = &clk->base.subdev; u32 target_clk_f, ref_clk_f, target_freq; u32 min_vco_f, max_vco_f; u32 low_pl, high_pl, best_pl; Loading Loading @@ -198,7 +199,7 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) } } nv_debug(clk, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); /* Select lowest possible VCO */ Loading Loading @@ -249,7 +250,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) WARN_ON(best_delta == ~0); if (best_delta != 0) nv_debug(clk, "no best match for target @ %dMHz on gpc_pll", nvkm_debug(subdev, "no best match for target @ %dMHz on gpc_pll", target_clk_f); clk->m = best_m; Loading @@ -258,7 +260,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) target_freq = gk20a_pllg_calc_rate(clk) / MHZ; nv_debug(clk, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", nvkm_debug(subdev, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]); return 0; } Loading @@ -266,7 +269,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) static int gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) { struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; u32 val; int ramp_timeout; Loading Loading @@ -314,7 +318,7 @@ gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN); if (ramp_timeout <= 0) { nv_error(clk, "gpcpll dynamic ramp timeout\n"); nvkm_error(subdev, "gpcpll dynamic ramp timeout\n"); return -ETIMEDOUT; } Loading @@ -340,7 +344,8 @@ _gk20a_pllg_disable(struct gk20a_clk *clk) static int _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) { struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; u32 val, cfg; u32 m_old, pl_old, n_lo; Loading Loading @@ -387,8 +392,8 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) _gk20a_pllg_disable(clk); nv_debug(clk, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n, clk->pl); nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n, clk->pl); n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, clk->parent_rate / MHZ); Loading Loading @@ -567,7 +572,8 @@ static int gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) { struct gk20a_clk *clk = container_of(obj, typeof(*clk), base); struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; switch (src) { case nv_clk_src_crystal: Loading @@ -576,7 +582,7 @@ gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) gk20a_pllg_read_mnp(clk); return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; default: nv_error(clk, "invalid clock source %d\n", src); nvkm_error(subdev, "invalid clock source %d\n", src); return -EINVAL; } } Loading Loading @@ -620,7 +626,8 @@ static int gk20a_clk_init(struct nvkm_object *object) { struct gk20a_clk *clk = (void *)object; struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; int ret; nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); Loading @@ -631,7 +638,7 @@ gk20a_clk_init(struct nvkm_object *object) ret = gk20a_clk_prog(&clk->base); if (ret) { nv_error(clk, "cannot initialize clock\n"); nvkm_error(subdev, "cannot initialize clock\n"); return ret; } Loading Loading @@ -665,7 +672,8 @@ gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, plat = nv_device_to_platform(nv_device(parent)); clk->parent_rate = clk_get_rate(plat->gpu->clk); nv_info(clk, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ); nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ); clk->base.read = gk20a_clk_read; clk->base.calc = gk20a_clk_calc; Loading
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +4 −3 Original line number Diff line number Diff line Loading @@ -139,7 +139,8 @@ static int gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) { struct gt215_clk *clk = container_of(obj, typeof(*clk), base); struct nvkm_device *device = clk->base.subdev.device; struct nvkm_subdev *subdev = &clk->base.subdev; struct nvkm_device *device = subdev->device; u32 hsrc; switch (src) { Loading Loading @@ -167,11 +168,11 @@ gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) case 3: return 277000; default: nv_error(clk, "unknown HOST clock source %d\n", hsrc); nvkm_error(subdev, "unknown HOST clock source %d\n", hsrc); return -EINVAL; } default: nv_error(clk, "invalid clock source %d\n", src); nvkm_error(subdev, "invalid clock source %d\n", src); return -EINVAL; } Loading