Commit b83a309a authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915/icl: Add Wa_1409178092 



We were missing this workaround which can cause hangs if fine grained
coherency was used.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717180624.20354-7-tvrtko.ursulin@linux.intel.com
parent 935ba6f3

drivers/gpu/drm/i915/gt/intel_workarounds.c

+6 −0
Original line number Diff line number Diff line
@@ -1297,6 +1297,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
		wa_write_or(wal,

			    GEN7_SARCHKMD,

			    GEN7_DISABLE_SAMPLER_PREFETCH);



		/* Wa_1409178092:icl */

		wa_write_masked_or(wal,

				   GEN11_SCRATCH2,

				   GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,

				   0);

	}



	if (IS_GEN_RANGE(i915, 9, 11)) {

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -7721,6 +7721,9 @@ enum { 
#define GEN7_L3SQCREG4				_MMIO(0xb034)

#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1 << 27)



#define GEN11_SCRATCH2					_MMIO(0xb140)

#define  GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE	(1 << 19)



#define GEN8_L3SQCREG4				_MMIO(0xb118)

#define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)

#define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)