Commit 935ba6f3 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4 



Having fixed the incorect MCR programming in an earlier patch, we can now
stop ignoring read back of GEN8_L3SQCREG4 during engine workaround
verification.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717180624.20354-6-tvrtko.ursulin@linux.intel.com
parent fa380486

drivers/gpu/drm/i915/gt/intel_workarounds.c

+6 −21
Original line number Diff line number Diff line
@@ -177,19 +177,6 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 
	wa_write_masked_or(wal, reg, val, val);

}



static void

ignore_wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)

{

	struct i915_wa wa = {

		.reg  = reg,

		.mask = mask,

		.val  = val,

		/* Bonkers HW, skip verifying */

	};



	_wa_add(wal, &wa);

}



#define WA_SET_BIT_MASKED(addr, mask) \

	wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
@@ -1260,9 +1247,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
			     _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);



		/* WaPipelineFlushCoherentLines:icl */

		ignore_wa_write_or(wal,

		wa_write_or(wal,

			    GEN8_L3SQCREG4,

				   GEN8_LQSC_FLUSH_COHERENT_LINES,

			    GEN8_LQSC_FLUSH_COHERENT_LINES);



		/*
@@ -1290,9 +1276,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
		 * Wa_1405733216:icl

		 * Formerly known as WaDisableCleanEvicts

		 */

		ignore_wa_write_or(wal,

		wa_write_or(wal,

			    GEN8_L3SQCREG4,

				   GEN11_LQSC_CLEAN_EVICT_DISABLE,

			    GEN11_LQSC_CLEAN_EVICT_DISABLE);



		/* WaForwardProgressSoftReset:icl */