Commit a54f4272 authored by Conor Dooley's avatar Conor Dooley
Browse files

riscv: dts: sifive: convert isa detection to new properties 



Convert the fu540 and fu740 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Reviewed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 561add0d

arch/riscv/boot/dts/sifive/fu540-c000.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ cpu0: cpu@0 { 
			i-cache-size = <16384>;

			reg = <0>;

			riscv,isa = "rv64imac";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",

					       "zihpm";

			status = "disabled";

			cpu0_intc: interrupt-controller {

				#interrupt-cells = <1>;
@@ -53,6 +56,9 @@ cpu1: cpu@1 { 
			mmu-type = "riscv,sv39";

			reg = <1>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;

			next-level-cache = <&l2cache>;

			cpu1_intc: interrupt-controller {
@@ -77,6 +83,9 @@ cpu2: cpu@2 { 
			mmu-type = "riscv,sv39";

			reg = <2>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;

			next-level-cache = <&l2cache>;

			cpu2_intc: interrupt-controller {
@@ -101,6 +110,9 @@ cpu3: cpu@3 { 
			mmu-type = "riscv,sv39";

			reg = <3>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;

			next-level-cache = <&l2cache>;

			cpu3_intc: interrupt-controller {
@@ -125,6 +137,9 @@ cpu4: cpu@4 { 
			mmu-type = "riscv,sv39";

			reg = <4>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;

			next-level-cache = <&l2cache>;

			cpu4_intc: interrupt-controller {

arch/riscv/boot/dts/sifive/fu740-c000.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -31,6 +31,9 @@ cpu0: cpu@0 { 
			next-level-cache = <&ccache>;

			reg = <0x0>;

			riscv,isa = "rv64imac";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",

					       "zihpm";

			status = "disabled";

			cpu0_intc: interrupt-controller {

				#interrupt-cells = <1>;
@@ -55,6 +58,9 @@ cpu1: cpu@1 { 
			next-level-cache = <&ccache>;

			reg = <0x1>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;

			cpu1_intc: interrupt-controller {

				#interrupt-cells = <1>;
@@ -79,6 +85,9 @@ cpu2: cpu@2 { 
			next-level-cache = <&ccache>;

			reg = <0x2>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;

			cpu2_intc: interrupt-controller {

				#interrupt-cells = <1>;
@@ -103,6 +112,9 @@ cpu3: cpu@3 { 
			next-level-cache = <&ccache>;

			reg = <0x3>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;

			cpu3_intc: interrupt-controller {

				#interrupt-cells = <1>;
@@ -127,6 +139,9 @@ cpu4: cpu@4 { 
			next-level-cache = <&ccache>;

			reg = <0x4>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;

			cpu4_intc: interrupt-controller {

				#interrupt-cells = <1>;