Commit 561add0d authored by Conor Dooley's avatar Conor Dooley
Browse files

riscv: dts: microchip: convert isa detection to new properties 



Convert the PolarFire SoC devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 1ce3a957

arch/riscv/boot/dts/microchip/mpfs.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -22,6 +22,9 @@ cpu0: cpu@0 { 
			i-cache-size = <16384>;

			reg = <0>;

			riscv,isa = "rv64imac";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",

					       "zihpm";

			clocks = <&clkcfg CLK_CPU>;

			status = "disabled";
@@ -48,6 +51,9 @@ cpu1: cpu@1 { 
			mmu-type = "riscv,sv39";

			reg = <1>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;
@@ -76,6 +82,9 @@ cpu2: cpu@2 { 
			mmu-type = "riscv,sv39";

			reg = <2>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;
@@ -104,6 +113,9 @@ cpu3: cpu@3 { 
			mmu-type = "riscv,sv39";

			reg = <3>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;
@@ -132,6 +144,9 @@ cpu4: cpu@4 { 
			mmu-type = "riscv,sv39";

			reg = <4>;

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;