Commit 88347fa1 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amdgpu: expose the minimum shader/memory clock frequency 



Otherwise, some UMD tools will treate them as 0 at default while
actually they are not.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5cfd9784

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+8 −2
Original line number Diff line number Diff line
@@ -785,9 +785,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
		if (adev->pm.dpm_enabled) {

			dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;

			dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;

			dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;

			dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;

		} else {

			dev_info->max_engine_clock = adev->clock.default_sclk * 10;

			dev_info->max_memory_clock = adev->clock.default_mclk * 10;

			dev_info->max_engine_clock =

				dev_info->min_engine_clock =

					adev->clock.default_sclk * 10;

			dev_info->max_memory_clock =

				dev_info->min_memory_clock =

					adev->clock.default_mclk * 10;

		}

		dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;

		dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *

include/uapi/drm/amdgpu_drm.h

+2 −0
Original line number Diff line number Diff line
@@ -1111,6 +1111,8 @@ struct drm_amdgpu_info_device { 
	__u32 pa_sc_tile_steering_override;

	/* disabled TCCs */

	__u64 tcc_disabled_mask;

	__u64 min_engine_clock;

	__u64 min_memory_clock;

};



struct drm_amdgpu_info_hw_ip {