Commit 86b20703 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: add xcc index argument to rlc safe_mode func (v4) 



v1: To support multple XCD case (Le)
v2: unify naming style (Le)
v3: apply the changes to gc v11_0 (Hawking)
v4: apply the changes to gc SOC21 (Morris)

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarMorris Zhang <Shiwu.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d51ac6d0

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c

+8 −8
Original line number Diff line number Diff line
@@ -34,9 +34,9 @@ 
 *

 * Set RLC enter into safe mode if RLC is enabled and haven't in safe mode.

 */

void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev)

void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	if (adev->gfx.rlc.in_safe_mode)

	if (adev->gfx.rlc.in_safe_mode[xcc_id])

		return;



	/* if RLC is not enabled, do nothing */
@@ -46,8 +46,8 @@ void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev) 
	if (adev->cg_flags &

	    (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |

	     AMD_CG_SUPPORT_GFX_3D_CGCG)) {

		adev->gfx.rlc.funcs->set_safe_mode(adev);

		adev->gfx.rlc.in_safe_mode = true;

		adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id);

		adev->gfx.rlc.in_safe_mode[xcc_id] = true;

	}

}
@@ -58,9 +58,9 @@ void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev) 
 *

 * Set RLC exit safe mode if RLC is enabled and have entered into safe mode.

 */

void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev)

void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	if (!(adev->gfx.rlc.in_safe_mode))

	if (!(adev->gfx.rlc.in_safe_mode[xcc_id]))

		return;



	/* if RLC is not enabled, do nothing */
@@ -70,8 +70,8 @@ void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev) 
	if (adev->cg_flags &

	    (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |

	     AMD_CG_SUPPORT_GFX_3D_CGCG)) {

		adev->gfx.rlc.funcs->unset_safe_mode(adev);

		adev->gfx.rlc.in_safe_mode = false;

		adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id);

		adev->gfx.rlc.in_safe_mode[xcc_id] = false;

	}

}

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

+5 −5
Original line number Diff line number Diff line
@@ -157,8 +157,8 @@ typedef struct _RLC_TABLE_OF_CONTENT { 


struct amdgpu_rlc_funcs {

	bool (*is_rlc_enabled)(struct amdgpu_device *adev);

	void (*set_safe_mode)(struct amdgpu_device *adev);

	void (*unset_safe_mode)(struct amdgpu_device *adev);

	void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);

	void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);

	int  (*init)(struct amdgpu_device *adev);

	u32  (*get_csb_size)(struct amdgpu_device *adev);

	void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
@@ -201,7 +201,7 @@ struct amdgpu_rlc { 
	u32                     cp_table_size;



	/* safe mode for updating CG/PG state */

	bool in_safe_mode;

	bool in_safe_mode[8];

	const struct amdgpu_rlc_funcs *funcs;



	/* for firmware data */
@@ -260,8 +260,8 @@ struct amdgpu_rlc { 
	struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl;

};



void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);

void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev);

void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id);

void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id);

int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);

int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);

int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+6 −6
Original line number Diff line number Diff line
@@ -7571,7 +7571,7 @@ static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 
	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

}



static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)

static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	uint32_t data;

	unsigned i;
@@ -7612,7 +7612,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 
	}

}



static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)

static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	uint32_t data;
@@ -7959,7 +7959,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d 
static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,

					    bool enable)

{

	amdgpu_gfx_rlc_enter_safe_mode(adev);

	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);



	if (enable) {

		/* enable FGCG firstly*/
@@ -7998,7 +7998,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
	     AMD_CG_SUPPORT_GFX_3D_CGLS))

		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);



	amdgpu_gfx_rlc_exit_safe_mode(adev);

	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);



	return 0;

}
@@ -8092,11 +8092,11 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 


static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)

{

	amdgpu_gfx_rlc_enter_safe_mode(adev);

	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);



	gfx_v10_cntl_power_gating(adev, enable);



	amdgpu_gfx_rlc_exit_safe_mode(adev);

	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);

}



static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+10 −10
Original line number Diff line number Diff line
@@ -123,8 +123,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 
static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,

					   uint16_t pasid, uint32_t flush_type,

					   bool all_hub, uint8_t dst_sel);

static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev);

static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);

static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);

static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);

static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,

				      bool enable);
@@ -4532,7 +4532,7 @@ static int gfx_v11_0_soft_reset(void *handle) 
	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);

	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);



	gfx_v11_0_set_safe_mode(adev);

	gfx_v11_0_set_safe_mode(adev, 0);



	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {

		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
@@ -4632,7 +4632,7 @@ static int gfx_v11_0_soft_reset(void *handle) 
	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);



	gfx_v11_0_unset_safe_mode(adev);

	gfx_v11_0_unset_safe_mode(adev, 0);



	return gfx_v11_0_cp_resume(adev);

}
@@ -4798,7 +4798,7 @@ static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 
	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

}



static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev)

static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	uint32_t data;

	unsigned i;
@@ -4817,7 +4817,7 @@ static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 
	}

}



static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev)

static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);

}
@@ -5045,7 +5045,7 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade 
static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,

					    bool enable)

{

	amdgpu_gfx_rlc_enter_safe_mode(adev);

	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);



	gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
@@ -5065,7 +5065,7 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
	     AMD_CG_SUPPORT_GFX_3D_CGLS))

	        gfx_v11_0_enable_gui_idle_interrupt(adev, enable);



	amdgpu_gfx_rlc_exit_safe_mode(adev);

	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);



	return 0;

}
@@ -5133,11 +5133,11 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 


static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)

{

	amdgpu_gfx_rlc_enter_safe_mode(adev);

	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);



	gfx_v11_cntl_power_gating(adev, enable);



	amdgpu_gfx_rlc_exit_safe_mode(adev);

	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);

}



static int gfx_v11_0_set_powergating_state(void *handle,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+2 −2
Original line number Diff line number Diff line
@@ -3362,7 +3362,7 @@ static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev) 
	return true;

}



static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev)

static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	u32 tmp, i, mask;
@@ -3384,7 +3384,7 @@ static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev) 
	}

}



static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev)

static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	u32 tmp;