Commit d51ac6d0 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: add xcc index argument to select_sh_se function v2 



v1: To support multiple XCD case (Le)
v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking)

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ec08571a

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+2 −2
Original line number Diff line number Diff line
@@ -787,7 +787,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, 
	for (se_idx = 0; se_idx < se_cnt; se_idx++) {

		for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {



			amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);

			amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff, 0);

			queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS);



			/*
@@ -820,7 +820,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, 
		}

	}



	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

	soc15_grbm_select(adev, 0, 0, 0, 0, 0);

	unlock_spi_csq_mutexes(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+8 −8
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, 
		}

		mutex_lock(&adev->grbm_idx_mutex);

		amdgpu_gfx_select_se_sh(adev, se_bank,

					sh_bank, instance_bank);

					sh_bank, instance_bank, 0);

	} else if (use_ring) {

		mutex_lock(&adev->srbm_mutex);

		amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
@@ -169,7 +169,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, 


end:

	if (use_bank) {

		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

		mutex_unlock(&adev->grbm_idx_mutex);

	} else if (use_ring) {

		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
@@ -263,7 +263,7 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 off 
		mutex_lock(&adev->grbm_idx_mutex);

		amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,

								rd->id.grbm.sh,

								rd->id.grbm.instance);

								rd->id.grbm.instance, 0);

	}



	if (rd->id.use_srbm) {
@@ -295,7 +295,7 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 off 
	}

end:

	if (rd->id.use_grbm) {

		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

		mutex_unlock(&adev->grbm_idx_mutex);

	}
@@ -907,13 +907,13 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, 


	/* switch to the specific se/sh/cu */

	mutex_lock(&adev->grbm_idx_mutex);

	amdgpu_gfx_select_se_sh(adev, se, sh, cu);

	amdgpu_gfx_select_se_sh(adev, se, sh, cu, 0);



	x = 0;

	if (adev->gfx.funcs->read_wave_data)

		adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);



	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);

	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);

	mutex_unlock(&adev->grbm_idx_mutex);



	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
@@ -1001,7 +1001,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, 


	/* switch to the specific se/sh/cu */

	mutex_lock(&adev->grbm_idx_mutex);

	amdgpu_gfx_select_se_sh(adev, se, sh, cu);

	amdgpu_gfx_select_se_sh(adev, se, sh, cu, 0);



	if (bank == 0) {

		if (adev->gfx.funcs->read_wave_vgprs)
@@ -1011,7 +1011,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, 
			adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);

	}



	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);

	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);

	mutex_unlock(&adev->grbm_idx_mutex);



	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+2 −2
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ struct amdgpu_gfx_funcs { 
	/* get the gpu clock counter */

	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);

	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,

			     u32 sh_num, u32 instance);

			     u32 sh_num, u32 instance, int xcc_id);

	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,

			       uint32_t wave, uint32_t *dst, int *no_fields);

	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
@@ -386,7 +386,7 @@ struct amdgpu_gfx { 
};



#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))

#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))

#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))

#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))

#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))

drivers/gpu/drm/amd/amdgpu/cik.c

+2 −2
Original line number Diff line number Diff line
@@ -1141,12 +1141,12 @@ static uint32_t cik_get_register_value(struct amdgpu_device *adev, 


		mutex_lock(&adev->grbm_idx_mutex);

		if (se_num != 0xffffffff || sh_num != 0xffffffff)

			amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);

			amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);



		val = RREG32(reg_offset);



		if (se_num != 0xffffffff || sh_num != 0xffffffff)

			amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

			amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

		mutex_unlock(&adev->grbm_idx_mutex);

		return val;

	} else {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+8 −8
Original line number Diff line number Diff line
@@ -3490,7 +3490,7 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 
				 struct amdgpu_cu_info *cu_info);

static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);

static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

				   u32 sh_num, u32 instance);

				   u32 sh_num, u32 instance, int xcc_id);

static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);



static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
@@ -4712,7 +4712,7 @@ static int gfx_v10_0_sw_fini(void *handle) 
}



static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,

				   u32 sh_num, u32 instance)

				   u32 sh_num, u32 instance, int xcc_id)

{

	u32 data;
@@ -4772,13 +4772,13 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 
				(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&

			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))

				continue;

			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);

			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);

			data = gfx_v10_0_get_rb_active_bitmap(adev);

			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *

					       rb_bitmap_width_per_sh);

		}

	}

	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

	mutex_unlock(&adev->grbm_idx_mutex);



	adev->gfx.config.backend_enable_mask = active_rbs;
@@ -4907,7 +4907,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 
	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);

			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);

			wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);

			/*

			 * Set corresponding TCP bits for the inactive WGPs in
@@ -4940,7 +4940,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 
		}

	}



	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

	mutex_unlock(&adev->grbm_idx_mutex);

}
@@ -9540,7 +9540,7 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 
			mask = 1;

			ao_bitmap = 0;

			counter = 0;

			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);

			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);

			if (i < 4 && j < 2)

				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(

					adev, disable_masks[i * 2 + j]);
@@ -9561,7 +9561,7 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 
			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;

		}

	}

	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);

	mutex_unlock(&adev->grbm_idx_mutex);



	cu_info->number = active_cu_number;