Commit 81b5948c authored by Conor Dooley's avatar Conor Dooley
Browse files

riscv: dts: starfive: convert isa detection to new properties 



Convert the jh7100 and jh7110 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent a54f4272

arch/riscv/boot/dts/starfive/jh7100.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -33,6 +33,9 @@ U74_0: cpu@0 { 
			i-tlb-size = <32>;

			mmu-type = "riscv,sv39";

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;



			cpu0_intc: interrupt-controller {
@@ -58,6 +61,9 @@ U74_1: cpu@1 { 
			i-tlb-size = <32>;

			mmu-type = "riscv,sv39";

			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			tlb-split;



			cpu1_intc: interrupt-controller {

arch/riscv/boot/dts/starfive/jh7110.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -28,6 +28,9 @@ S7_0: cpu@0 { 
			i-cache-size = <16384>;

			next-level-cache = <&ccache>;

			riscv,isa = "rv64imac_zba_zbb";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",

					       "zifencei", "zihpm";

			status = "disabled";



			cpu0_intc: interrupt-controller {
@@ -54,6 +57,9 @@ U74_1: cpu@1 { 
			mmu-type = "riscv,sv39";

			next-level-cache = <&ccache>;

			riscv,isa = "rv64imafdc_zba_zbb";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",

					       "zicsr", "zifencei", "zihpm";

			tlb-split;

			operating-points-v2 = <&cpu_opp>;

			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -84,6 +90,9 @@ U74_2: cpu@2 { 
			mmu-type = "riscv,sv39";

			next-level-cache = <&ccache>;

			riscv,isa = "rv64imafdc_zba_zbb";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",

					       "zicsr", "zifencei", "zihpm";

			tlb-split;

			operating-points-v2 = <&cpu_opp>;

			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -114,6 +123,9 @@ U74_3: cpu@3 { 
			mmu-type = "riscv,sv39";

			next-level-cache = <&ccache>;

			riscv,isa = "rv64imafdc_zba_zbb";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",

					       "zicsr", "zifencei", "zihpm";

			tlb-split;

			operating-points-v2 = <&cpu_opp>;

			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -144,6 +156,9 @@ U74_4: cpu@4 { 
			mmu-type = "riscv,sv39";

			next-level-cache = <&ccache>;

			riscv,isa = "rv64imafdc_zba_zbb";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",

					       "zicsr", "zifencei", "zihpm";

			tlb-split;

			operating-points-v2 = <&cpu_opp>;

			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;