Commit 5d238510 authored by Peng Ju Zhou's avatar Peng Ju Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: indirect register access for nv12 sriov 



using the control bits got from host to control registers access.

Signed-off-by: default avatarPeng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: default avatarEmily.Deng <Emily.Deng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 77eabc6f

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+2 −0
Original line number Diff line number Diff line
@@ -466,6 +466,8 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 
			((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;

		adev->virt.gim_feature =

			((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;

		adev->virt.reg_access =

			((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all;



		break;

	default:

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+17 −0
Original line number Diff line number Diff line
@@ -228,6 +228,7 @@ struct amdgpu_virt { 
	bool tdr_debug;

	struct amdgpu_virt_ras_err_handler_data *virt_eh_data;

	bool ras_init_done;

	uint32_t reg_access;



	/* vf2pf message */

	struct delayed_work vf2pf_work;
@@ -249,6 +250,22 @@ struct amdgpu_virt { 
#define amdgpu_sriov_fullaccess(adev) \

(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))



#define amdgpu_sriov_reg_indirect_en(adev) \

(amdgpu_sriov_vf((adev)) && \

	((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))



#define amdgpu_sriov_reg_indirect_ih(adev) \

(amdgpu_sriov_vf((adev)) && \

	((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))



#define amdgpu_sriov_reg_indirect_mmhub(adev) \

(amdgpu_sriov_vf((adev)) && \

	((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))



#define amdgpu_sriov_reg_indirect_gc(adev) \

(amdgpu_sriov_vf((adev)) && \

	((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))



#define amdgpu_passthrough(adev) \

((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)