Commit 52e844ee authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

arm64: dts: reneas: rzg2: Add SDnH clocks 



Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-9-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-10-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-11-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-12-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f9a2adcc

arch/arm64/boot/dts/renesas/r8a774a1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2276,7 +2276,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2288,7 +2289,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2300,7 +2302,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2312,7 +2315,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

arch/arm64/boot/dts/renesas/r8a774b1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2133,7 +2133,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2145,7 +2146,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2157,7 +2159,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2169,7 +2172,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+6 −3
Original line number Diff line number Diff line
@@ -1626,7 +1626,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -1638,7 +1639,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -1650,7 +1652,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

arch/arm64/boot/dts/renesas/r8a774e1.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -2362,7 +2362,8 @@ sdhi0: mmc@ee100000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee100000 0 0x2000>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 314>;
@@ -2375,7 +2376,8 @@ sdhi1: mmc@ee120000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee120000 0 0x2000>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 313>;

			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 313>;
@@ -2388,7 +2390,8 @@ sdhi2: mmc@ee140000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee140000 0 0x2000>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 312>;
@@ -2401,7 +2404,8 @@ sdhi3: mmc@ee160000 { 
				     "renesas,rcar-gen3-sdhi";

			reg = <0 0xee160000 0 0x2000>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;

			clock-names = "core", "clkh";

			max-frequency = <200000000>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 311>;