Commit f9a2adcc authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes 



Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211109123110.8543-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5a8aa63c

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -266,6 +266,36 @@ scif4: serial@1004c800 { 
			status = "disabled";

		};



		sci0: serial@1004d000 {

			compatible = "renesas,r9a07g044-sci", "renesas,sci";

			reg = <0 0x1004d000 0 0x400>;

			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "eri", "rxi", "txi", "tei";

			clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;

			clock-names = "fck";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_SCI0_RST>;

			status = "disabled";

		};



		sci1: serial@1004d400 {

			compatible = "renesas,r9a07g044-sci", "renesas,sci";

			reg = <0 0x1004d400 0 0x400>;

			interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "eri", "rxi", "txi", "tei";

			clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;

			clock-names = "fck";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_SCI1_RST>;

			status = "disabled";

		};



		canfd: can@10050000 {

			compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";

			reg = <0 0x10050000 0 0x8000>;