Commit 4a2e9d11 authored by Dafna Hirschfeld's avatar Dafna Hirschfeld Committed by Oded Gabbay
Browse files

accel/habanalabs: don't trace cpu accessible dma alloc/free 



The cpu accessible dma allocations use the gen_pool api which actually
does not allocate new memory from the system but manages memory already
allocated before. When tracing this together with real dma
allocation/free it cause confusing logs like a '0' dma address and
a cpu address appearing twice etc.

Signed-off-by: default avatarDafna Hirschfeld <dhirschfeld@habana.ai>
Reviewed-by: default avatarOded Gabbay <ogabbay@kernel.org>
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
Reviewed-by: default avatarStanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
parent 1d0f9ad7

drivers/accel/habanalabs/common/device.c

+10 −19
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 


enum dma_alloc_type {

	DMA_ALLOC_COHERENT,

	DMA_ALLOC_CPU_ACCESSIBLE,

	DMA_ALLOC_POOL,

};
@@ -121,9 +120,6 @@ static void *hl_dma_alloc_common(struct hl_device *hdev, size_t size, dma_addr_t 
	case DMA_ALLOC_COHERENT:

		ptr = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, size, dma_handle, flag);

		break;

	case DMA_ALLOC_CPU_ACCESSIBLE:

		ptr = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);

		break;

	case DMA_ALLOC_POOL:

		ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, size, flag, dma_handle);

		break;
@@ -147,9 +143,6 @@ static void hl_asic_dma_free_common(struct hl_device *hdev, size_t size, void *c 
	case DMA_ALLOC_COHERENT:

		hdev->asic_funcs->asic_dma_free_coherent(hdev, size, cpu_addr, dma_handle);

		break;

	case DMA_ALLOC_CPU_ACCESSIBLE:

		hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, size, cpu_addr);

		break;

	case DMA_ALLOC_POOL:

		hdev->asic_funcs->asic_dma_pool_free(hdev, cpu_addr, dma_handle);

		break;
@@ -170,28 +163,26 @@ void hl_asic_dma_free_coherent_caller(struct hl_device *hdev, size_t size, void 
	hl_asic_dma_free_common(hdev, size, cpu_addr, dma_handle, DMA_ALLOC_COHERENT, caller);

}



void *hl_cpu_accessible_dma_pool_alloc_caller(struct hl_device *hdev, size_t size,

void *hl_asic_dma_pool_zalloc_caller(struct hl_device *hdev, size_t size, gfp_t mem_flags,

					dma_addr_t *dma_handle, const char *caller)

{

	return hl_dma_alloc_common(hdev, size, dma_handle, 0, DMA_ALLOC_CPU_ACCESSIBLE, caller);

	return hl_dma_alloc_common(hdev, size, dma_handle, mem_flags, DMA_ALLOC_POOL, caller);

}



void hl_cpu_accessible_dma_pool_free_caller(struct hl_device *hdev, size_t size, void *vaddr,

void hl_asic_dma_pool_free_caller(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr,

					const char *caller)

{

	hl_asic_dma_free_common(hdev, size, vaddr, 0, DMA_ALLOC_CPU_ACCESSIBLE, caller);

	hl_asic_dma_free_common(hdev, 0, vaddr, dma_addr, DMA_ALLOC_POOL, caller);

}



void *hl_asic_dma_pool_zalloc_caller(struct hl_device *hdev, size_t size, gfp_t mem_flags,

					dma_addr_t *dma_handle, const char *caller)

void *hl_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle)

{

	return hl_dma_alloc_common(hdev, size, dma_handle, mem_flags, DMA_ALLOC_POOL, caller);

	return hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);

}



void hl_asic_dma_pool_free_caller(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr,

					const char *caller)

void hl_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr)

{

	hl_asic_dma_free_common(hdev, 0, vaddr, dma_addr, DMA_ALLOC_POOL, caller);

	hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, size, vaddr);

}



int hl_dma_map_sgtable(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir)

drivers/accel/habanalabs/common/habanalabs.h

+2 −10
Original line number Diff line number Diff line
@@ -155,18 +155,12 @@ enum hl_mmu_enablement { 
#define hl_asic_dma_alloc_coherent(hdev, size, dma_handle, flags) \

	hl_asic_dma_alloc_coherent_caller(hdev, size, dma_handle, flags, __func__)



#define hl_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle) \

	hl_cpu_accessible_dma_pool_alloc_caller(hdev, size, dma_handle, __func__)



#define hl_asic_dma_pool_zalloc(hdev, size, mem_flags, dma_handle) \

	hl_asic_dma_pool_zalloc_caller(hdev, size, mem_flags, dma_handle, __func__)



#define hl_asic_dma_free_coherent(hdev, size, cpu_addr, dma_handle) \

	hl_asic_dma_free_coherent_caller(hdev, size, cpu_addr, dma_handle, __func__)



#define hl_cpu_accessible_dma_pool_free(hdev, size, vaddr) \

	hl_cpu_accessible_dma_pool_free_caller(hdev, size, vaddr, __func__)



#define hl_asic_dma_pool_free(hdev, vaddr, dma_addr) \

	hl_asic_dma_pool_free_caller(hdev, vaddr, dma_addr, __func__)
@@ -3602,14 +3596,12 @@ static inline bool hl_mem_area_crosses_range(u64 address, u32 size, 
}



uint64_t hl_set_dram_bar_default(struct hl_device *hdev, u64 addr);

void *hl_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle);

void hl_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr);

void *hl_asic_dma_alloc_coherent_caller(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle,

					gfp_t flag, const char *caller);

void hl_asic_dma_free_coherent_caller(struct hl_device *hdev, size_t size, void *cpu_addr,

					dma_addr_t dma_handle, const char *caller);

void *hl_cpu_accessible_dma_pool_alloc_caller(struct hl_device *hdev, size_t size,

						dma_addr_t *dma_handle, const char *caller);

void hl_cpu_accessible_dma_pool_free_caller(struct hl_device *hdev, size_t size, void *vaddr,

						const char *caller);

void *hl_asic_dma_pool_zalloc_caller(struct hl_device *hdev, size_t size, gfp_t mem_flags,

					dma_addr_t *dma_handle, const char *caller);

void hl_asic_dma_pool_free_caller(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr,