Commit 4398ab23 authored by Marian-Cristian Rotariu's avatar Marian-Cristian Rotariu Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a774e1: Add VSP instances 



The RZ/G2H (R8A774E1) has 6 VSP instances.

Based on the work done for r8a7795 SoC.

Signed-off-by: default avatarMarian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200810092208.27320-3-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a3855ebc

arch/arm64/boot/dts/renesas/r8a774e1.dtsi

+66 −0
Original line number Diff line number Diff line
@@ -2376,6 +2376,72 @@ pciec1: pcie@ee800000 { 
			status = "disabled";

		};



		vspbc: vsp@fe920000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe920000 0 0x8000>;

			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 624>;

			power-domains = <&sysc R8A774E1_PD_A3VP>;

			resets = <&cpg 624>;



			renesas,fcp = <&fcpvb1>;

		};



		vspbd: vsp@fe960000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe960000 0 0x8000>;

			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 626>;

			power-domains = <&sysc R8A774E1_PD_A3VP>;

			resets = <&cpg 626>;



			renesas,fcp = <&fcpvb0>;

		};



		vspd0: vsp@fea20000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea20000 0 0x5000>;

			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 623>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 623>;



			renesas,fcp = <&fcpvd0>;

		};



		vspd1: vsp@fea28000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea28000 0 0x5000>;

			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 622>;

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 622>;



			renesas,fcp = <&fcpvd1>;

		};



		vspi0: vsp@fe9a0000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe9a0000 0 0x8000>;

			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 631>;

			power-domains = <&sysc R8A774E1_PD_A3VP>;

			resets = <&cpg 631>;



			renesas,fcp = <&fcpvi0>;

		};



		vspi1: vsp@fe9b0000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe9b0000 0 0x8000>;

			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 630>;

			power-domains = <&sysc R8A774E1_PD_A3VP>;

			resets = <&cpg 630>;



			renesas,fcp = <&fcpvi1>;

		};



		fcpf0: fcp@fe950000 {

			compatible = "renesas,fcpf";

			reg = <0 0xfe950000 0 0x200>;