Transforms are new unit of modularity within the compiler.

Add unit tests for splitting expressions and padding widths

RemoveValidIf, SplitExpressions, and PadWidths

This is to start moving stuff out of Emitter and into separate passes

Changed initialization to assign the correct number of random bits.

Fixes #133

Fixes #113 and Fixes #150

Make EmptyExpression part of WIR

Change Field from IsDeclaration to HasName

Make WDefInstance an IsDeclaration

time uses LazyLogging, also delete import PrimOps._ (cyclic reference)

Fixed the check for bundle equality to allow relative flips to be wrong, but the leaf directions are the same

Added flag to parser to turn off using source locators. This allows for easier testing, because we don't the source locator information to say a test fails

Also add pass to Verilog Compiler list of passes

This pass appends '_' to the names of aggregate types that would cause a name collision during LowerTypes.