HTTPS clone is with .git; cd only with no error.

SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).

* Added Zero width wires.

Semantics:
 - No change to width inference rules, e.g.
     a<0> + b<2> = c<3>
 - Replace zero width wires with UInt<1>(0) or SInt<1>(0)
 - Performs constant prop.
 - Redo width/type inference

* Remove errant println

* Moved ZeroWidth after ConvertFixedToSInt

* Added more tests, bugfix match on connect

Also replaced constprop with infertypes for correctness

* Updated to new emitter and test infrastructure

Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.

Changes Emitters to also be Transforms and use Annotations for both
telling an emitter to do emission as well as getting the emitted result.
Helper functions ease the use of the new interface. Also adds a
FirrtlExecutionOptions field as well as a command-line option. Use of 
Writers in Compilers and Emitters is now deprecated.

Workaround for #470. This allows parsing DoubleLits in subfield
expressions.

* castrhs shouldn't assume rhs is uint

* don't cast if types are the same

* changed castrhs to catch invalid lhs, rhs type combinations

* change error msg

Also remove parsing support for ids with characters not supported in
Verilog nor in the Firrtl spec

The fix for PR #305 caused a new compile warning from Cadence Incisive:

  always @(*) begin end
         |
ncelab: *W,STARMT (../TestHarness.MyConfig.v,196147|9): This @* expands to empty list, will never wake up.

This change satisfies all of: VCS, Incisive, Questa, Vivado, Verilator.

This allows the replseqmem transform to not deduplicate
some memories, based on their name.

Also add support for width inference