* Updated FIRRTL spec + related code for readwrite ports.
    (write) data -> wdata & mask -> wmask for clarity

* Also removed simple.fir that snuck into master branch.

Now prints usage when given incorrect arguments

Also added clock to reg's abstract syntax

Added help string #234

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

Add missing case for connecting ClockType

fix read port enables in RemoveCHIRRTL
LGTM -chick

read port enables for cmems should always be high

Don't create output files until the compiler succeeds

Creating the output file preemptively screws up make, as on
subsequent executions of make, it thinks the task succeeded.

Bugfix: recursing stmts to remove unknown widths

* Added RemoveEmpty.scala, which removes Empty and nested Blocks

* Reused squashEmpty from ExpandWhens by moving it to Utils

* Squash EmptyStmts in ExpandWhens correctly

Change serialize to abstract method on FirrtlNode

Fix mem infer

turned on with '--inferRW <circuit name>'

Fix use of global state in instance loop checking

Change default log level to warn

Refactor RemoveAccesses and fix bug #210.

Also increase sensitivity of thread safety checking
Fixes #159

remove ConstProp in HighFirrtlToMiddleFirrtl

Fix StringSpec generators to only choose from valid values.

Added corresponding unit test.

The old almost equivalent syntax gives the same result but can cause the
test to fail if too many invalid values are thrown away.

ConstProp before width padding causes errors for SIntLiteral

InferWidths now only fixes declaration widths

Then calls InferTypes to propagate inferred widths to expressions.
Required upgrading InferTypes to do simple width propagation.
Fixes #206  and #200.