Fix minor regression from #1124

Implement read-first memory behavior in Verilog

* Corrects behavior under write collisions
* Avoids heavily refactoring pass

* Stop ignoring read-under-write (RUW) parameter
* Add conservative check: blackbox only when RUW is "undefined"
* VerilogMemDelays now throws InternalError for read-first memories
* Previously, read-first mems were incorrectly implemented as write-first

* Make the read-under-write (RUW) parameter typesafe
* Add RUW support to the FIRRTL proto and CHIRRTL grammar

* Define read-write collison for independently clocked mem ports

* Included definition of initiating write/read operation

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* dont chain inline and refix RenameMaps

* cache already inlined modules

* reduce number of chained RenameMaps

* InlineInstances: cleanup and add comments

Create instance maps once for each Module

Gender to Flow

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

The following names are changed:
  - gender        -> flow
  - Gender        -> Flow
  - MALE          -> SourceFlow
  - FEMALE        -> SinkFlow
  - BIGENDER      -> DuplexFlow
  - UNKNOWNGENDER -> UnknownFlow

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Copy benchmark.py from https://github.com/jackkoenig/firrtlbench
* Make benchmark use this repo instead of hardcoded subdirectory

Example Use:
  benchmark/scripts/benchmark_cold_compile.py -N 8 --designs regress/*.fir --version master master^

* Update Travis stage names to match new versions

* Drop minor versions from Travis stage names and delete old comment

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Adds a space to correct in an exception message. Corrects
capitalization in Github to it's official name (GitHub) and adds a
link to file an issue.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Refactor: remove redundancy code

* Fixed coding style

Programmed Stage Death

This adds the StageError Error. This Error indicates that a
Stage/Phase has hit an unrecoverable error, it cannot continue, and
requests that the entire Stage/Phase hierarchy be killed with an
ExitFailure ExitCode. StageMain is modified to catch StageError and
exit the application with the provided exit code number.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Remove incorrect short option for --info-mode

This should be a helpValueName and not a shortOption.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1>
* Enhance async reset initial value literal check to support aggregates

Improve RemoveReset on Invalid Inits

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This modifies RemoveReset to NOT generate a mux for
invalid (IsInvalid) inits. In the case of an invalid init, the reset
is converted to a self-connect and no mux is generated.

This is implemented as a new, initial pass over the module to populate
a set of all invalid signals. During the subsequent, circuit-modifying
pass, this invalid set is queried to special case the handling of
invalid inits.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>