Fixes bug with mul or div followed by cat.
Also fixes some Verilog lint issues.

* Check Unidoc on all versions of Scala

  It is required for publishing and we publish every version

* Fix conflicting cross-version suffixes issue

  When running `sbt ++2.13.4 unidoc`, SBT would set the Scala version
  for the fuzzer and benchmark projects even though they aren't really
  relevant to the command. This may be a misconfiguration or a bug in
  the unidoc plugin. Whatever the case, simply making it possible for
  them to use the same version of Scala as the firrtl project (on which
  they depend) fixes the issue.

* Match versions of Scala in build.sbt and CI

* Fix unidoc issues in 2.13.4

  There is some bug in ScalaDoc not finding some links in firrtl.options
  so those links were made absolute as a workaround.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This adds a --dont-fold options (backed by a DisableFold annotation)
that lets a user specify primitive operations which should never be
folded. This feature lets a user disable certain folds which may be
allowable in FIRRTL (or by any sane synthesis tool), but due to inane
Verilog language design causes formal equivalence tools to fail due to
the fold.

Add a test that a user can disable `a / a -> 1` with a
DisableFold(PrimOps.Div) annotation.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Fix scalafmtCheckAll failures that snuck through

* Fix .run_formal_checks for Github Actions instead of Travis
* Remove .run_chisel_tests

Because we publish SNAPSHOTs on every merge to master, the Chisel repo
checks against master of FIRRTL regularly

* Only run unidoc for Scala 2.12

Under Travis we ran for 2.11, 2.12, and 2.13, but it doesn't work when
using ++2.<major>.<minor> when major != to 2.12. It seems if we want to
run all 3, we have to run as `sbt +unidoc`. It's not clear how much
benefit we get from building on the other versions, so stick with 2.12
for now.

* Generate .mergify.yml with script in chisel-repo-tools

Generated with config:

conditions:
  - status-success=all tests passed
branches:
  - 1.2.x
  - 1.3.x
  - 1.4.x

This is done by having LowerTypes uses two RenameMaps instead of one for
each module. There is one for renaming instance paths, and one for
renaming everything within modules.

Also add some utilities:
* TargetUtils for dealing with InstanceTargets
* RenameMap.fromInstanceRenames

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

This is now set by sbt-ci-release

sbt-ci-release changes the commands required to publish to Sonatype.
While this may be a desirable change at some point, it is inconsistent
with other repos. Reverting for the time being.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* add test for RemoveAccessesSpec.

* fix nested SubAccess bug.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add SortModules to transform to def-before-use

Adds a new transform, SortModules, that transforms a FIRRTL circuit
to enforce an invariant of modules and external modules being defined
before use. This transform is left as optional in the event that a
user may wish to have a quick way of getting the circuit to respect
this property as may be expected of some other tool, e.g., MLIR.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add test of SortModules transform

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Verilator 4.034 was complaining about wires being named weak and strong
because those are SV 2009 keywords.  Added them to the Utils.v_keywords list

* Make MultiTargetAnnotation.targets a def

This enables the annotation writer to choose their own underlying data structure

* Update MultiTargetAnnotation ScalaDoc

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Seq[(Int, DoPrimGen)] to Map[ExprGen[_ <: Expression], Int]

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Uses sbt-ci-release for automation

It would replace them with a validif node with a UIntLiteral which can
lead to type errors.

* smt: add test for write port collision

* smt: add missing call to insertDummyAssignsForMemoryOutputs

* smt: fix typo in write port code

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* split big Emitter to submodules.

* fix all deprecated warning.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* smt: add tests for assert name clashes

* smt: ensure unique signal names with a namespace

this fixes issues #1934

Fix verilog prep

* Make Stage.run protected

Change the access modifier of Stage.run from no modifier to protected.
This method is really an internal API that the user implements with
the main entry point for a Stage being "execute" or "transform". By
allowing users to access "run" they can bypass checks, mandatory file
reads/writes, and wrappers.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Make FirrtlStage.run protected

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>