* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter

Fixes #329

Fixed Verilog emission reduce ops with efficient implementation

Change FixedPointMathSpec tests to use FlatSpec style instead of println
Remove other printlns
Remove vim comments at end of files

* Keep package name + directory structure consistent

This annoyed me so heres a PR

* fix InferReadWrite references

* delete .ConvertFixedToSInt.scala.swo

Added wiring pass and simple test

* fix imports in InferReadWrite

* improve reference & name resolution in ReplSeqMem

* add comments

While unsafe, this supports Verilog parameter types.
Tests now require Verilator 3.884+ to pass.

Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.

Change integration tests to be classes that extend abstract classes. This
allows them to be run in parallel. Also expand API to support Verilog
resources in integration tests.

* Create a simple system for executions and command line parameters
New model for tracking parameters and having those parameters
register scopt command to allow the parameters to be set by
command line args.
Create composable forms of the these parameters to allow separate
elements of the chisel3 toolchain to combine these parameters
Create execution return structures that simplify return values
to earlier toolchain elements

* just a little bit of cleanup

* Fixes for Adam's comments on PR

* knuckled under to self-pressure to allow former -i and -o to work

* knuckled under to self-pressure to allow former -i and -o to work

* show defaults for command line args with them

* A couple of fixes from merging latest master

* Implement a log4scala like logging system
This system has the rather remarkable property
that it is possible to turn it on conveniently when
you want it.  It also provides for class level granularity
as well as the traditional Error, Warn, Info, Debug

* some style fixes and change infoMode default to append per PR #328

* some style fixes and change infoMode default to append per PR #328

* support -i -o and -X
a couple of indentation and spacing fixes

* toBitMask cat direction should be consistent with data

* minor comment updates

* moved remaining mem passes/utils to memlib

* changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated

duplcate memory detection should be in circuit-level, not in module-level

Chisel now depends on Firrtl so we need to publish to run Chisel tests

annotations are now being passed down to firrtl compiler

Fixes colin's problem with repl-seq-mem not creating a conf file.

Create a simple system for executions and command line parameters
New model for tracking parameters and having those parameters
register scopt command to allow the parameters to be set by
command line args.

Create composable forms of the these parameters to allow separate
elements of the chisel3 toolchain to combine these parameters
Create execution return structures that simplify return values
to earlier toolchain elements

* Reorganized memory blackboxing

Moved to new package memlib
Added comments
Moved utility functions around
Removed unused AnnotateValidMemConfigs.scala

* Fixed tests to pass

* Use DefAnnotatedMemory instead of AppendableInfo

* Broke passes up into simpler passes

AnnotateMemMacros ->
  (ToMemIR, ResolveMaskGranularity)
UpdateDuplicateMemMacros ->
  (RenameAnnotatedMemoryPorts, ResolveMemoryReference)

* Fixed to make tests run

* Minor changes from code review

* Removed vim comments and renamed ReplSeqMem

* WIP: Adding FixedType to Firrtl proper

Got simple example running through width inference
Checks should be ok
Need to look into FixedLiteral more

* Added simple test for fixed types

* Added asFixedPoint to primops

* Added tail case for FixedType

* Added ConvertFixedToSInt.scala

Added pass to MiddleToLowerFirrtl transform

* Replace AsFixedType with AsSInt in fixed removal

* Bugfix: constant from asFixed not deleted

* Added unit test for bulk connect

* Fixed partial connect bug #241

* Fixed missing case for FixedPoint in legalizeConnect

* Add FixedMathSpec that demonstrates some problems with FixedPointMath

* Fixed test and ConvertToSInt to pass.

Negative binary points not easily supported, needs much more time to
implement.

* Refactored checking neg widths

Make checking for negative binary points easier

* Added tests for inferring many FixedType ops

shl, shr, cat, bits, head, tail, setbp, shiftbp

* Handle bpshl, bpshr, bpset in ConvertFixedToSInt

Changed name from shiftbp -> bpshl, bpshr
Change name from setbp -> bpset
Added more tests

* Added set binary point test that fails

* Added simple test for zero binary point

* gitignore fixes for antlr intermediate dir and intellij dir

* removed unused imports
retool the fixed point with zero binary point test

* simplified example of inability to set binary point to zero

* Temporary fix for zero-width binary point

This fix allows for all widths to be zero, but since this is a feature I
am working on next, I'm not going to bother with a more stringent check.

* change version for dsp tools

* Removed extra temporary file

* Fixed merge bug

* Fixed another merge bug

* Removed commented out/unrelated files

* Removed snake case

* working through variable shrouding

* working through variable shrouding

* working through variable shadowing

* working through variable shadowing
hmm there are some very fragile match {} in Passes

* working through variable shadowing
hmm there are some very fragile match {} in Passes

* working through variable shadowing

* working through variable shadowing

* working through variable shadowing

* working through variable shadowing

* working through variable shadowing

* working through variable shadowing

* working through variable shadowing

* working through variable shadowing

* Fixes suggested by Adam

this makes it much easier to see where something
went wrong during compilation if the lines have
no info initially or its on internal nodes

Fix CInferMDir

indices should be read ports

Address #297

* Spec features added: AnalogType and Attach

AnalogType(width: Width):
  - Concrete syntax:
      wire x: AnalogType<10>
  - New groundtype, very restricted in use cases.
  - Can only declare ports and wires with Analog type
  - Analog types are never equivalent, thus if x and y have Analog
    types: x <= y is never legal.

Attach(info: Info, source: Expression, exprs: Seq[Expression]):
  - Concrete syntax:
      attach x to (y, z)
  - New statement
  - Source can be any groundtyped expression (UInt, SInt, Analog, Clock)
  - Exprs must have an Analog type reference an instance port
  - Source and exprs must have identical widths

Included WDefInstanceConnector to enable emission of Verilog inout
Should be mostly feature complete.
Need to update spec if PR gets accepted.

* Fixed bug where invalidated ports aren't handled

* Bugfix for VerilogPrep

Intermediate wires for invalidated instance ports were not invalidated

* Bugfix: calling create_exp with name/tpe

Returns unknown gender, which was passing through
Caused temporary wire to not be declared
Because Verilog is dumb, undeclared wires are assumed to be 1bit signals

* Addressed donggyukim's style comments

* Reworked pass to only allow analog types in attach

Restrict source to be only wire or port kind
Much simpler implementation, almost identical functionality
Clearer semantics (i think?)

* Fixup bugs from pulling in new changes from master

* comments for type eqs and small style fixes

Mem latency pipes

discussed with @azidar