Fixes #409 

Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.

This means CSE need only be run once to get same QOR and prevents
pathological cases. Fixes #448

Fixes bug where arbitrary expressions, if called with .expr, return the
same expression.

Also add GlobalCircuitAnnotation for creating similar annotations

Now remove DefNodes of zero width
Don't deeply walk nodes (was the source of the bug)

Use newer rocket regression spec without comb loop

HTTPS clone is with .git; cd only with no error.

SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).

* Added Zero width wires.

Semantics:
 - No change to width inference rules, e.g.
     a<0> + b<2> = c<3>
 - Replace zero width wires with UInt<1>(0) or SInt<1>(0)
 - Performs constant prop.
 - Redo width/type inference

* Remove errant println

* Moved ZeroWidth after ConvertFixedToSInt

* Added more tests, bugfix match on connect

Also replaced constprop with infertypes for correctness

* Updated to new emitter and test infrastructure