0. replace AnnotatedMemoriesCollectorAnnotation with immutable
   AnnotatedMemoriesAnnotation.
1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute.

0. rewrite CreateMemoryAnnotations to correct file to match
   ReplSeqMemAnnotation to create PinAnnotation.
1. add DumpMemoryAnnotations to convert from
   AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation
2. refactor MemLibOutConfigFileAnnotation and remove
   HasAnnotatedMemories
3. add private AnnotatedMemoriesCollectorAnnotation to store mutable
   DefAnnotatedMemory
4. change ReplSeqMem to SeqTransform

0. Since DependencyAPI only initiate transform only once, ListBuffer is
   dangerous to use, remove defAnnotatedMemories from Transform.
1. Add trait HasAnnotatedMemories to store ListBuffer,
   MemLibOutConfigFileAnnotation also extends from which now.

Looks like a typo/auto-merge hiccup.

Co-authored-by: jackkoenig <jackkoenig@users.noreply.github.com>

With Stage/Phase, users can provide complex functionality at the phase
level rather than just the transform level. It is useful to have the
same logging information at that level. Note that this change still logs
transforms in the same way, but now the time in inclusive of annotation
renaming which can also [unfortunately] be slow.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fixes #2173

Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:

    circuit Foo :
      module Foo :
        input a: UInt<3>
        output b: UInt<4>
        b <= asUInt(xor(asSInt(a), SInt<4>(0)))

This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.

This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.

Also make minor updates to CI workflow

Using Utils.indent() gives deprecation warnings to use Serializer instead. However,
the Serializer class itself doesn't provide a means to manually indent a FirrtlNode
string a certain number of times.

The indent variable, previously hardcoded to 0, is now exposed as a second parameter
for the modified serialize function, and the old serialize function just calls the
modified serialize with indents = 0 for binary compatibility

Co-authored-by: Megan Wachs <megan@sifive.com>

* bitWidth: add scaladoc

* smt: use existing bitWidth API

To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)

* Update name of FPGA flag based on Jack's comment
* Add Scaladoc to describe what each constituent transform does
* Add SeparateWriteClocks to --target:fpga

* Address @ekiwi comments from review
* Change match cases to scalafmt-mandated lined-up style

* Update test to include both 'old' and 'new' read-under-write values

* Optionally defines read-under-write behavior for all 'undefined' memories
* Use DefaultReadFirstAnnotation to choose read-first default
* Use DefaultWriteFirstAnnotation to choose write-first default
* Seal DefaultReadUnderWriteAnnotation based on Jack's feedback

* This is enabled by adding a PassthroughSimpleSyncReadMemsAnnotation
* Can be emitted directly with new changes to the Verilog emitter
* Add some new deprecations to VerilogMemDelays
* Run scalafmt on VerilogMemDelays

* Emit readwrite ports, if applicable
* Does not change VerilogMemDelays -> no effect on default flow
* Use more single-line declare-and-assign statements for mem wires
* Update error messages for too-complex memories in VerilogEmitter
* Run scalafmt on VerilogEmitter

This PR adds options for memory initialization inside or outside the
`ifndef SYNTHESIS` block.

* Fix Mill support for non-M1 Macs

* Update build.sc

Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com>

Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com>