Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

We never tested the case where the width of the
numerator was less than the denominator.
This should fix any issue with this combination.

+ correct the Error Info of "At least one dedupable annotation..."

Reset, AsyncReset, Interval, attach, assert, assume, and cover have all
been added as keywords but not added to the allowlist for parsing as
ids.

Hotfix for Vector Reg Init LegalizeConnects Bug

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add a private pass, LegalizeConnectsOnly, that behaves like
LegalizeConnects, but only pads connects instead of connects and
register inits.  Padding is necessary for ReplSeqMem, but ReplSeqMem
runs before LowerTypes and vector registers can still exist at this
point.  Connects, conversely, are all blown out by ExpandConnects and
can be safely, blindly treated as ground type.

Fixes #2379.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Demonstrate a couple failing cases

* Have TopWiring ignore unnamed declarations as potential sources

* Have Flatten & InlineInstances remove their annotations

* Format

* Added RTLIL Backend.

* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.

* Fix build on scala 2.13

* Add additional equivalence test, make some bugfixes and perf opts to the emitter.

* Final changes as requested by Kevin, code cleanup, add support for formal cells.

8abf3085

 reordered the fields, but it
unintentionally placed a closing brace before the actual end of the
write port type. This moves the brace to the end of the port.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

The test was leaving the test directory in a dirty state that would fail
on a rerun. Fix the test so that it can be run multiple times in a row.

This required also bumping sbt-scalafix to bring in a newer version of
semanticdb. The new version of semanticdb had an issue with a regex in
SMTLib, fixed by fixing the way '$' is escaped in the regex.

BlackBoxSourceHelper should only run late in compilation to allow
transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).

* Add compiler option (`-p`) to emit individual module protobufs
* Implement multi module combination when reading directory of protobufs

Co-authored-by: Jack Koenig <koenig@sifive.com>

We treat it as an assertion that the stop will
never be enabled. stop(0) will still be ignored
(but now demoted to a info from a warning).

* Fix dshl zero-width shift behavior

Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Fix dshl zero-width shift behavior

Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize
file emission.

* If exist protoc in the $PATH, prefer to using it.

* add checkSystemAntlr4Version and checkSystemProtocVersion

* Update build.sc

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

to make it has the same form with NoDCEAnnotation and NoConstantPropagationAnnotation

This will make it easier for formal verification
libraries to make use of these emitters.

Both transforms are (most likely) not needed.

The SMT backend actually needs to run PropagatePresetAnnotations
(as will treadle at some point).
None of the Verilog specific passes were actually required!

* implement NoCommonSubexpressionElimination to resolve chipsalliance/chisel3#2006

* Update src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>